LTC6820
17
6820fb
For more information www.linear.com/LTC6820
OPERATION
Table 5. I
DD
Equations
STATE MSTR ESTIMATED I
DD
IDLE 0 (slave) 2µA
1 (master) 1µA
READY 0 or 1 1.7mA + 3 • I
B
ACTIVE 0 (slave)
2mA + 3 + 20 •
100ns • 0.5
t
CLK
•I
B
1 (master)
2mA + 3 +20 •
100ns
t
CLK
•I
B
IDLE Mode and Wake-Up Detection
To conserve power, an LTC6820 in slave mode (MSTR=0)
will enter an IDLE state after 5.7ms (t
IDLE
) of inactivity
on the IP/IM pins. In this condition I
DD
is reduced to less
than 6µA and the SPI pins are idled (CS = 1, MOSI = 1
and SCK = POL).
The LTC6820 will continue monitoring the IP and IM
pins using a low power AC-coupled detector. It will wake
up when it sees a differential signal of 240mV or greater
that persists for 240ns or longer. In practice, a long (CS)
isoSPI pulse is sufficient to wake the device up. Once the
comparator generates the wake-up signal it can take up
to 8µs (t
READY
) for bias circuits to stabilize.
Figure 14 details the sequence of waking up a slave LTC6820
(placing it in the READY state), using it to communicate,
then allowing it to return to the low power IDLE state.
A LTC6820 in master mode (MSTR = 1) doesn’t use the
wake-up detection comparator. A falling edge on CS will
enable the isoSPI port within t
READY
, and the LTC6820
will transmit a long (CS) pulse as it leaves the IDLE state.
(The polarity of the pulse matches the CS state at the end
of t
READY
).
The master LTC6820 will remain in the READY/ACTIVE
state as long as CS = 0. If CS transitions high and EN=0
it will enter the IDLE state, but not until t
IDLE
expires.
This prevents the device from shutting down between
data packets.
In either master or slave mode the IDLE feature may be
disabled by driving EN high. This forces the device to
remain “ready” at all times.
Figure 15 demonstrates a simple procedure for waking
a master (MSTR = 1) LTC6820 and its connected slave
(MSTR = 0). A negative edge on CS causes the master
to drive IBIAS to 2V and, after a short delay, transmit a
long +1 pulse. (If CS remains low throughout t
READY
, the
LTC6820 would first generate a –1 pulse, then the +1
pulse when CS returns high). The long pulse serves as a
wake-up signal for the slave device, which responds by
driving its IBIAS pin to 2V and entering the READY state.
|IP
AC
–IM
AC
| > 240mV
IP
AC
IM
AC
WAKE-UP
IP
240mV
IM
EN
CS
240ns
240ns DELAY
(FILTER)
SLAVE
MASTER
t
READY
t
IDLE
IDLE TIMER
READY
(IBIAS = 2V)
6820 F13
Figure 13. Wake-Up Detection and IDLE Timer
Figure 14. Slave LTC6820 Wake-Up/Idle Timing
Figure 15. Master and Slave Wake-Up/Idle Sequence
COMMON MODE
NOISE
IP
IM
IP-IM
t
DWELL
t
READY
t
IDLE
OK TO COMMUNICATE
SLAVE CS
SLAVE
IBIAS
IP-IM
MASTER
IBIAS
CS
t
DWELL
READY
MASTER AND SLAVE
t
READY
t
IDLE
t
IDLE
t
READY
