IDT8N4SV75 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO
IDT8N4SV75CCD
REVISION B NOVEMBER 6, 2013
12 ©2013 Integrated Device Technology, Inc.
Schematic Layout
Figure 2 shows an example of IDT8N4SV75 application schematic.
In this example, the device is operated at V
DD
= 3.3V. As with any
high speed analog circuitry, the power supply pins are vulnerable to
random noise. To achieve optimum jitter performance, power supply
isolation is required.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1µF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure that the logic control inputs are
properly set.
Figure 2. IDT8N4SV75 Schematic Example
R1
100
Set Logic
Input to
'1'
R3
50
J1
1
2
Set Logic
Input to
'0'
3.3V
U1
1
2
3 4
5
6
VC
OE
VEE Q
nQ
VCC
nQ
Alternate
LVDS
Termination
Q
To Logic
Input
pins
BLM18BB221SN1
Ferrite Bead
1 2
C4
0.1uF
Logic Control Input Examples
VDD
VC
OE
VDD
R1
SP
nQ
+
-
VDD=3.3V
Zo_Diff = 100 Ohm
+
-
RU1
1K
RD2
1K
Q
RD1
Not Install
RU2
Not Install
C3
0.1uF
R4
SP
VDD
C1
0.1uF
LVDS Termination
VDD
To Logic
Input
pins
C2
10uF
R2
50
Zo_Diff = 100 Ohm
