IDT8N4SV75 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO
IDT8N4SV75CCD
REVISION B NOVEMBER 6, 2013
13 ©2013 Integrated Device Technology, Inc.
Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8N4SV75.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the IDT8N4SV75 is the sum of the core power plus the analog power plus the power dissipated due to the load.
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
•Power
MAX
= V
CC_MAX
* I
CC_MAX
= 3.465V * 175mA = 606mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 49.4°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.606mW * 49.4°C/W = 114.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance
JA
for a 6-Lead Ceramic 5mm x 7mm Package, Forced Convection
JA
by Velocity
Meters per Second 012
Multi-Layer PCB, JEDEC Standard Test Boards 49.4°C/W 44.2°C/W 42.1°C/W
