31
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 9. Write Queue Select, Write Operation and Full Flag Operation
WCLK
WADEN
t
QH
t
QS
t
AH
t
AS
WRADD
Q
x
FF
t
WFF
5941 drw12
WEN
t
ENS
t
AH
t
AS
Q
y
t
QH
t
QS
t
DH
t
DS
Q
X
W
D
t
DH
Q
y
W
D-2
W
D-1
Q
y
t
DH
Din
t
WFF
t
WFF
Previous Q Status
No Writes
Queue Full
*A* *B* *C* *D* *E* *F* *G*
t
DS
Q
y
W
D
t
DS
t
DH
t
ENH
t
WFF
t
WFF
RCLK
t
SKEW1
t
QS
t
QH
REN
t
ENS
RDADD
Q
y
RADEN
Qout
t
A
Previous Q, Word, W Previous Q, W
+1
PFT
t
A
Qy, W
0
PFT
t
A
t
A
Qy, W
1
Qy, W
2
*H* *I* *J*
t
AS
t
AH
*AA* *BB* *CC* *DD
*
*EE* *FF*
t
DS
NOTE:
OE is active LOW.
Cycle:
*A* Queue, Qx is selected on the write port.
The FF flag is providing status of a previously selected queue, within the same device.
*AA* Queue, Qy is selected for read operations.
*B* The FF flag output updates to show the status of Qx, it is not full.
*BB* Word W+1 is read from the previous queue regardless of REN due to FWFT.
*C* Word, Wd is written into Qx. This causes Qx to go full.
*CC* Word, W0 is read from Qy regardless of REN, this is due to the FWFT effect.
*D* Queue, Qy is selected within the same device as Qx. A write to Qx cannot occur on this cycle because it is full, FF is LOW.
*DD* No reads occur, REN is HIGH.
*E* Again, a write to Qx cannot occur on this cycle because it is full, FF is LOW. The FF flag updates after time t
WFF to show that queue, Qy is not full.
*EE* Word, W1 is read from Qy, this causes Qy to go “not full”, FF flag goes HIGH after time, t
SKEW1 + tWFF. Note, if tSKEW1 is violated the time FF HIGH will be: tSKEW1 + WCLK + tWFF.
*F* Word, Wd-2 is written into Qy.
*FF* Word, W2 is read from Qy.
*G* Word, Wd-1 is written into Qy.
*H* Word, Wd is written into Qy, this causes Qy to go full, FF goes LOW.
*I* No writes occur to Qy.
*J* Qy goes “not full” based on reading word W1 from Qy on cycle *EE*.
32
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
5941 drw12a
W1 W2 W3
WCLK
t
ENH
WEN
Dn
t
DH
t
DS
t
DS
t
DH
t
DS
t
DH
RCLK
t
SKEW1
12
tENS
REN
t
A
W1 Qy
FWFT
t
A
t
A
W2 Qy
FWFT
W3 QyLast Word Read Out of Queue
Qout
t
ROV
OV
t
ROV
t
ENS
Figure 10. Write Operations & First Word Fall Through
NOTES:
1. Qy has previously been selected on both the write and read ports.
2. OE is LOW.
3. The First Word Latency = tSKEW1 + RCLK + tA. If tSKEW1 is violated an additional RCLK cycle must be added.
33
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK
WADEN
t
QH
t
QS
t
AH
t
AS
WRADD
D
1
Q
3
FF
(Device 1)
t
FFLZ
5941 drw13
WEN
t
ENS
t
AH
t
AS
t
AH
t
AS
t
QH
t
QS
D
2
Q
2
t
QH
t
QS
t
DH
t
DS
W
D
D
1 Q3
t
DH
t
DS
Din
t
WFF
t
WFF
HIGH-Z
RCLK
1
2
t
ENH
t
ENS
t
ENH
Addr=00111
D
1
Q
0
t
WFF
W
D
D
1 Q0
t
FFHZ
t
WFF
HIGH-Z
FF
(Device 2)
t
FFHZ
HIGH-Z
t
FFLZ
t
SKEW1
Addr=00100
t
AH
t
AS
RDADD
D
1
Q
0
t
QH
t
QS
RADEN
*A* *B* *C* *D* *E* *F* *G* *H* *I*
No Write
*J*
Qout
t
A
t
A
Previous Q W
X-1
Previous Q W
X
PFT
D
1
-Q
0
Word W
0
PFT
*AA* *BB* *CC*
Addr=01010
Addr=001000
Figure 11. Full Flag Timing in Expansion Mode
NOTE:
1. REN = HIGH.
Cycle:
*A* Queue, Q3 of device 1 is selected on the write port.
The FF flag of device 1 is in High-Impedance, the write port of device 2 was previously selected.
WEN is HIGH so no write occurs.
*AA* Queue, Q0 of device 1 is selected on the read port.
*B* The FF flag of device 2 goes to High-Impedance and the FF flag of device 1 goes to Low-Impedance, logic HIGH indicating that D1 Q3 is not full.
WEN is HIGH so no write occurs.
*BB* Word, Wx is read from the previously selected queue, (due to FWFT).
*C* Word, Wd is written into Q3 of D1. This write operation causes Q3 to go full, FF goes LOW.
*CC* The first word from Q0 of D1 selected on cycle *AA* is read out, this occurred regardless of REN due to FWFT. This read caused Q0 to go not full, therefore the FF flag will go HIGH after: t
SKEW1 + tWFF.
Note if t
SKEW1 is violated the time to FF flag HIGH is tSKEW1 + WLCK + tWFF.
*D* Queue, Q0 of device 1 is selected on the write port. No write occurs on this cycle.
*E* The FF flag updates to show the status of D1 Q0, it is not full, FF goes HIGH.
*F* Word, Wd is written into Q0 of D1. This causes the queue to go full, FF goes LOW.
*G* No write occurs regardless of WEN, the FF flag is LOW preventing writes.
*H* The FF flag goes HIGH due to the read from Q0 of D1 on cycle *CC*. (This read is not an enabled read, it is due to the FWFT operation).
*I* Queue, Q2 of device 2 is selected on the write port.
*J* The FF flag of device 1 goes to High-Impedance, this device was deselected on the write port on cycle *I*. The FF flag of device 2 goes to Low-Impedance and provides status of Q2 of D2.

72V51253L6BB

Mfr. #:
Manufacturer:
IDT
Description:
FIFO X18 4Q 2M MULTI-QUE
Lifecycle:
New from this manufacturer.
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