5
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DETAILED DESCRIPTION
MULTI-QUEUE STRUCTURE
The IDT multi-queue flow-control device has a single data input port and
single data output port with up to 4 FIFO queues in parallel buffering between
the two ports. The user can setup between 1 and 4 Queues within the device.
These queues can be configured to utilize the total available memory, providing
the user with full flexibility and ability to configure the queues to be various depths,
independent of one another.
MEMORY ORGANIZATION/ ALLOCATION
The memory is organized into what is known as “blocks”, each block being
512 x 18 or 1,024 x 9 bits. When the user is configuring the number of queues
and individual queue sizes the user must allocate the memory to respective
queues, in units of blocks, that is, a single queue can be made up from 0 to m
blocks, where m is the total number of blocks available within a device. Also the
total size of any given queue must be in increments of 512 x 18 or 1,024 x 9.
For the IDT72V51233, IDT72V51243 and IDT72V51253 the Total Available
Memory is 64, 128 and 256 blocks respectively (a block being 512 x 18 or 1,024
x 9). If any port is configured for x18 bus width, a block size is 512 x 18. If both
the write and read ports are configured for x9 bus width, a block size is 1,024
x 9. Queues can be built from these blocks to make any size queue desired and
any number of queues desired.
BUS WIDTHS
The input port is common to all queues within the device, as is the output port.
The device provides the user with Bus Matching options such that the input port
and output port can be either x9 or x18 bits wide, the read and write port widths
being set independently of one another. Because the ports are common to all
queues the width of the queues is not individually set, so that the input width of
all queues are equal and the output width of all queues are equal.
WRITING TO & READING FROM THE MULTI-QUEUE
Data being written into the device via the input port is directed to a discrete
queue via the write queue select address inputs. Conversely, data being read
from the device read port is read from a queue selected via the read queue select
address inputs. Data can be simultaneously written into and read from the same
queue or different queues. Once a queue is selected for data writes or reads,
the writing and reading operation is performed in the same manner as
conventional IDT synchronous FIFO, utilizing clocks and enables, there is a
single clock and enable per port. When a specific queue is addressed on the
write port, data placed on the data inputs is written to that queue sequentially
based on the rising edge of a write clock provided setup and hold times are met.
Conversely, data is read on to the output port after an access time from a rising
edge on a read clock.
The operation of the write port is comparable to the function of a conventional
FIFO operating in standard IDT mode. Write operations can be performed on
the write port provided that the queue currently selected is not full, a full flag output
provides status of the selected queue. The operation of the read port is
comparable to the function of a conventional FIFO operating in FWFT mode.
When a queue is selected on the output port, the next word in that queue will
automatically fall through to the output register. All subsequent words from that
queue require an enabled read cycle. Data cannot be read from a selected
queue if that queue is empty, the read port provides an Output Valid flag indicating
when data read out is valid. If the user switches to a queue that is empty, the
last word from the previous queue will remain on the output register.
As mentioned, the write port has a full flag, providing full status of the selected
queue. Along with the full flag a dedicated almost full flag is provided, this almost
full flag is similar to the almost full flag of a conventional IDT FIFO. The device
provides a user programmable almost full flag for all 4 queues and when a
respective queue is selected on the write port, the almost full flag provides status
for that queue. Conversely, the read port has an output valid flag, providing
status of the data being read from the queue selected on the read port. As well
as the output valid flag the device provides a dedicated almost empty flag. This
almost empty flag is similar to the almost empty flag of a conventional IDT FIFO.
The device provides a user programmable almost empty flag for all 4 queues
and when a respective queue is selected on the read port, the almost empty flag
provides status for that queue.
PROGRAMMABLE FLAG BUSSES
In addition to these dedicated flags, full & almost full on the write port and output
valid & almost empty on the read port, there are two flag status busses. An almost
full flag status bus is provided, this bus is 4 bits wide. Also, an almost empty flag
status bus is provided, again this bus is 4 bits wide. The purpose of these flag
busses is to provide the user with a means by which to monitor the data levels
within queues that may not be selected on the write or read port. As mentioned,
the device provides almost full and almost empty registers (programmable by
the user) for each of the 4 queues in the device.
The 4 bit PAEn and 4 bit PAFn busses provide a discrete status of the Almost
Empty and Almost Full conditions of all 4 queue's. If the device is programmed
for less than 4 queue's, then there will be a corresponding number of active
outputs on the PAEn and PAFn busses.
The flag busses can provide a continuous status of all queues. If devices are
connected in expansion mode the individual flag busses can be left in a discrete
form, providing constant status of all queues, or the busses of individual devices
can be connected together to produce a single bus of 4 bits. The device can
then operate in a "Polled" or "Direct" mode.
When operating in polled mode the flag bus provides status of each device
sequentially, that is, on each rising edge of a clock the flag bus is updated to show
the status of each device in order. The rising edge of the write clock will update
the Almost Full bus and a rising edge on the read clock will update the Almost
Empty bus.
When operating in direct mode the device driving the flag bus is selected by
the user. The user addresses the device that will take control of a respective
flag bus, these PAFn and PAEn flag busses operating independently of one
another. Addressing of the Almost Full flag bus is done via the write port and
addressing of the Almost Empty flag bus is done via the read port.
EXPANSION
Expansion of multi-queue devices is also possible, up to 8 devices can be
connected in a parallel fashion providing the possibility of both depth expansion
or queue expansion. Depth Expansion means expanding the depths of
individual queues. Queue expansion means increasing the total number of
queues available. Depth expansion is possible by virtue of the fact that more
memory blocks within a multi-queue device can be allocated to increase the
depth of a queue. For example, depth expansion of 8 devices provides the
possibility of 8 queues of 32K x 18 deep within the IDT72V51233, 64K x 18 deep
within the IDT72V51243 and 128K x 18 deep within the IDT72V51253, each
queue being setup within a single device utilizing all memory blocks available
to produce a single queue. This is the deepest queue that can setup within a
device.
For queue expansion of the 4 queue device, a maximum number of 32 (8
x 4) queues may be setup, each queue being 4K x18 or 2K x 9 deep, if less
queues are setup, then more memory blocks will be available to increase queue
depths if desired. When connecting multi-queue devices in expansion mode all
respective input pins (data & control) and output pins (data & flags), should be
“connected” together between individual devices.
