9
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RDADD Read Address Bus LVTTL on the RDADD bus will be selected on a rising edge of RCLK provided that RADEN is HIGH, (note, that
[5:0] INPUT data can be placed on to the Qout bus, read from the previously selected queue on this RCLK edge).
(Continued) On the next rising RCLK edge after a read queue select, a data word from the previous queue will be
(RDADD5-P16 placed onto the outputs, Qout, regardless of the REN input. Two RCLK rising edges after read queue
RDADD4-P15 select, data will be placed on to the Qout outputs from the newly selected queue, regardless of REN due
RDADD3-P14 to the first word fall through effect.
RDADD2-N14 The second function of the RDADD bus is to select the device of queues to be loaded on to the PAEn
RDADD1-M16 bus during strobed flag mode. The most significant 3 bits, RDADD[5:3] are again used to select 1 of 8
RDADD0-M15) possible multi-queue devices that may be connected in expansion mode. Address bits RDADD[2:0] are
don’t care during device selection. The device address present on the RDADD bus will be selected on the
rising edge of RCLK provided that ESTR is HIGH, (note, that data can be placed on to the Qout bus, read
from the previously selected queue on this RCLK edge). Please refer to Table 2 for details on RDADD bus.
REN Read Enable LVTTL The REN input enables read operations from a selected queue based on a rising edge of RCLK. A
(T11) INPUT queue to be read from can be selected via RCLK, RADEN and the RDADD address bus regardless
of the state of REN. Data from a newly selected queue will be available on the Qout output bus on the second
RCLK cycle after queue selection regardless of REN due to the FWFT operation. A read enable is not
required to cycle the PAEn bus (in polled mode) or to select the device , (in direct mode).
SCLK Serial Clock LVTTL If serial programming of the multi-queue device has been selected during master reset, the SCLK input
(N3) INPUT clocks the serial data through the multi-queue device. Data setup on the SI input is loaded into the device
on the rising edge of SCLK provided that SENI is enabled, LOW. When expansion of devices is performed
the SCLK of all devices should be connected to the same source.
SENI Serial Input Enable LVTTL During serial programming of a multi-queue device, data loaded onto the SI input will be clocked into the
(M2) INPUT part (via a rising edge of SCLK), provided the SENI input of that device is LOW. If multiple devices are
cascaded, the SENI input should be connected to the SENO output of the previous device. So when serial
loading of a given device is complete, its SENO output goes LOW, allowing the next device in the chain
to be programmed (SENO will follow SENI of a given device once that device is programmed). The SENI
input of the master device (or single device), should be controlled by the user.
SENO Serial Output LVTTL This output is used to indicate that serial programming or default programming of the multi-queue device
(M1) Enable OUTPUT has been completed. SENO follows SENI once programming of a device is complete. Therefore, SENO
will go LOW after programming provided SENI is LOW, once SENI is taken HIGH again, SENO will also
go HIGH. When the SENO output goes LOW, the device is ready to begin normal read/write operations.
If multiple devices are cascaded and serial programming of the devices will be used, the SENO output
should be connected to the SENI input of the next device in the chain. When serial programming of the
first device is complete, SENO will go LOW, thereby taking the SENI input of the next device LOW and
so on throughout the chain. When a given device in the chain is fully programmed the SENO output
essentially follows the SENI input. The user should monitor the SENO output of the final device in the chain.
When this output goes LOW, serial loading of all devices has been completed.
SI Serial In LVTTL During serial programming this pin is loaded with the serial data that will configure the multi-queue devices.
(L1) INPUT Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion
mode the serial data input is loaded into the first device in a chain. When that device is loaded and its SENO
has gone LOW, the data present on SI will be directly output to the SO output. The SO pin of the first device
connects to the SI pin of the second and so on. The multi-queue device setup registers are shift registers.
SO Serial Out LVTTL This output is used in expansion mode and allows serial data to be passed through devices in the chain
(M3) OUTPUT to complete programming of all devices. The SI of a device connects to SO of the previous device in the
chain. The SO of the final device in a chain should not be connected.
TCK
(2)
JTAG Clock LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test
(A8) INPUT operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge
of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs
to be tied to GND.
TDI
(2)
JTAG Test Data LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
(B9) Input INPUT operation,test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register,
ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
PIN DESCRIPTIONS (CONTINUED)
Symbol & Name I/O TYPE Description
Pin No.
