40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
WCLK
Dn
Prev PAEn
RCLK
ESTR
RDADD
Device 5
101 xxx100 011
D5Q3
t
AH
t
AS
t
AH
t
AS
1
t
SKEW3
Previous value loaded on to PAE bus
1xxx
Device 5
2
RADEN
t
QH
t
QS
t
STH
t
STS
t
PAE
5941 drw24
Device 5 PAE
t
RAE
*AA* *BB* *CC*
*DD*
*FF**EE*
t
RAE
D5 Qx Status
Bus PAEn
Previous value loaded on to PAE bus
Device 5
t
PAEHZ
t
PAEZL
1xxx
REN
t
ENH
t
ENS
Device 5 -Qn
Wy
D5 Q3
Wy+1
D5 Q3
Wy+3
D5 Q3
Wy+2
D5 Q3
Wa+1
D5 Qn
t
A
t
A
t
A
t
A
t
A
Wa
D5 Qx
t
DH
t
DS
WEN
WADEN
FSTR
t
AH
100 11
t
AS
WRADD D5Q3
D3Q2
Wn
D5 Q3
Wn+1
D5Q3
Wx
D3 Q2
01110
Device 4
100 xx
*A* *B* *C* *D* *E* *F*
t
QH
t
QS
t
QH
t
QS
t
AH
t
AS
t
AH
t
AS
t
ENS
t
ENH
t
STH
t
STS
Device 5 PAEn
1
2
t
ENS
t
ENH
Wp+1
Wp
Writes to Previous Q
t
DH
t
DS
t
RAE
D5 Q3
status
1xxx
Device 5
Device 5
1xxx
Figure 22.
PAEPAE
PAEPAE
PAE
n - Direct Mode, Flag Operation – Devices in Expansion
Cycle:
*A* Queue 3 of Device 5 is selected for write operations.
Word, Wp is written into the previously selected queue.
*AA* Queue 3 of Device 5 is selected for read operations.
Another device has control of the PAEn bus.
The discrete PAE output of device 5 is currently in High-Impedance and the PAE active flag is controlled by the previously selected device.
*B* Word Wp+1 is written into the previously selected queue.
*BB* Word, Wa+1 is read from Qx of D5, due to FWFT operation.
*C* Word, Wn is written into the newly selected queue, Q3 of D5. This write will cause the PAE flag on the read port to go from LOW to HIGH (not almost empty) after time,
tSKEW3 + RCLK + tRAE (if tSKEW3 is violated one extra RCLK cycle will be added.
*CC* Word, Wy from the newly selected queue, Q3 will be read out due to FWFT operation.
Device 5 is selected on the PAEn bus. Q3 of device 5 will therefore have is PAE status output on PAE[3]. There is a single RCLK cycle latency before the PAEn bus changes
to the new selection.
*D* Queue 2 of Device 3 is selected for write operations.
Word Wn+1 is written into Q3 of D5.
*DD* The PAEn bus changes control to D5, the PAEn outputs of D5 go to Low-Impedance and are placed onto the outputs. The previously selected device now places its
PAEn outputs into High-Impedance to prevent bus contention. Word, Wy+1 is read from Q3 of D5.
The discrete PAE flag will go HIGH to show that Q3 of D5 is not almost empty. Q3 of device 5 will have its PAE status output on PAE[3].
*E* No writes occur.
*EE* Word, Wy+2 is read from Q3 of D5.
*F* Device 4 is selected on the write port for the PAFn bus.
Word, Wx is written into Q2 of D3.
*FF* The PAEn bus updates to show that Q3 of D5 is almost empty based on the reading out of word, Wy+1.
The discrete PAE flag goes LOW to show that Q3 of D5 is almost empty based on the reading of Wy+1.
