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IDT71V3557SA85BQGI8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
6.4210
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Functional Timing Diagram
(1)
Linear Burst Sequence Table (LBO=VSS)
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
NOTES:
1. This assumes CEN, CE1, CE2 and CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
n+29
A29
C29
D/Q28
ADDRESS
(A
0
-A
16
)
CONTROL
(R/W,ADV/LD, BWx)
DATA
I/O [0:31], I/O P[1:4]
C
Y
CLE
CLOCK
n+30
A30
C30
D/Q29
n+31
A31
C31
D/Q30
n+32
A32
C32
D/Q31
n+33
A33
C33
D/Q32
n+34
A34
C34
D/Q33
n+35
A35
C35
D/Q34
n+36
A36
C36
D/Q35
n+37
A37
C37
D/Q36
5282 drw 03
(2)
(2)
(2)
,
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11000110
5282 tbl 11
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
11
NOTES:
1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
2. H = High; L = Low; X = Don't Care; Z = High Impedence.
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles
(2)
Cycle Address R/W ADV/LD
CE
1
(1 )
CEN BWx OE
I/O Comments
nA
0
HL LLXXD
1
Load read
n+1 X X H X L X L Q
0
Burst read
n+2 A
1
HL LLXLQ
0+1
Load read
n+3 X X L H L X L Q
1
Deselect or STOP
n+4 X X H X L X X Z NOOP
n+5 A
2
H L L L X X Z Load read
n+6 X X H X L X L Q
2
Burst read
n+7 X X L H L X L Q
2+1
Deselect or STOP
n+8 A
3
L L LLLXZLoad write
n+9 X X H X L L X D
3
Burst write
n+10 A
4
L L LLLXD
3+1
Load write
n+11 X X L H L X X D
4
Deselect or STOP
n+12 X X H X L X X Z NOOP
n+13 A
5
L L LLLXZLoad write
n+14 A
6
HL LLXXD
5
Load read
n+15 A
7
L L LLLLQ
6
Load write
n+16 X X H X L L X D
7
Burst write
n+17 A
8
HL LLXXD
7+1
Load read
n+18 X X H X L X L Q
8
Burst read
n+19 A
9
L L LLLLQ
8+1
Load write
5282 tbl 12
6.4212
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Read Operation
(1)
Burst Write Operation
(1)
Burst Read Operation
(1)
Write Operation
(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Cycle Address R/W ADV/LD
CE
1
(2 )
CEN BWx OE
I/O Comments
nA
0
H L L L X X X Address and Control meet setup
n+1 X X X X X X L Q
0
Contents of Address A
0
Read Out
5282 tbl 13
Cycle Address R/W ADV/LD
CE
1
(2 )
CEN BWx OE
I/O Comments
nA
0
H L L L X X X Address and Control meet setup
n+1 X X H X L X L Q
0
Address A
0
Read Out, Inc. Count
n+2 X X H X L X L Q
0+1
Address A
0+1
Read Out, Inc. Count
n+3 X X H X L X L Q
0+2
Address A
0+2
Read Out, Inc. Count
n+4 X X H X L X L Q
0+3
Address A
0+3
Read Out, Load A
1
n+5 A
1
HL LLXLQ
0
Address A
0
Read Out, Inc. Count
n+6 X X H X L X L Q
1
Address A
1
Read Out, Inc. Count
n+7 A
2
HL LLXLQ
1+1
Address A
1+1
Read Out, Load A
2
5282 tbl 14
Cycle Address R/W ADV/LD
CE
1
(2 )
CEN BWx OE
I/O Comments
nA
0
L L L L L X X Address and Control meet setup
n+1 X X X X L X X D
0
Write to Address A
0
5282 tbl 15
Cycle Address R/W ADV/LD
CE
1
(2 )
CEN BWx OE
I/O Comments
nA
0
L L L L L X X Address and Control meet setup
n+1 X X H X L L X D
0
Address A
0
Write, Inc. Count
n+2 X X H X L L X D
0+1
Address A
0+1
Write, Inc. Count
n+3 X X H X L L X D
0+2
Address A
0+2
Write, Inc. Count
n+4 X X H X L L X D
0+3
Address A
0+3
Write, Load A
1
n+5 A
1
L L LLLXD
0
Address A
0
Write, Inc. Count
n+6 X X H X L L X D
1
Address A
1
Write, Inc. Count
n+7 A
2
L L LLLXD
1+1
Address A
1+1
Write, Load A
2
5282 tbl 16
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

IDT71V3557SA85BQGI8

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IC SRAM 4.5M PARALLEL 165CABGA
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