6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
21
Timing Waveform of CS Operation
(1,2,3,4)
NOTES:
1. Q (A
1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3 etc.
2. CE
2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. When either one of the Chip enables (CE
1, CE2, CE2) is sampled inactive at the rising clock edge, a deselect cycle is initiated. The data-bus tri-states one cycle after the initiation of the deselect
cycle. This allows for any pending data transfers (reads or writes) to be completed.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before
the actual data is presented to the SRAM.
R
/
W
A
1
C
L
K
A
D
V
/
L
D
A
D
D
R
E
S
S
C
E
1
,
C
E
2
(
2
)
O
E
D
A
T
A
O
U
T
Q
(
A
1
)
Q
(
A
2
)
Q
(
A
4
)
t
C
L
Z
Q
(
A
5
)
t
C
D
t
C
H
Z
t
C
D
C
D
(
A
3
)
t
S
D
t
H
D
t
C
H
t
C
L
t
C
Y
C
t
H
C
t
S
C
A
5
A
3
t
S
B
D
A
T
A
I
N
t
H
E
t
S
E
A
2
t
H
A
t
S
A
A
4
t
H
W
t
S
W
t
H
B
C
E
N
t
H
A
D
V
t
S
A
D
V
5
2
8
2
d
r
w
1
0
B
W
1
-
B
W
4
B
(
A
3
)
.
,
