6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
9
Interleaved Burst Sequence Table (LBO=VDD)
Partial Truth Table for Writes
(1)
Synchronous Truth Table
(1)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state one cycle after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for x18 configuration.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
CEN
R/W
CE
1
,
CE
2
(5)
ADV/LD
BWx
ADDRESS
USED
PREVIOUS CYCLE CURRENT CYCLE I/O
(One cycle later)
LL L L ValidExternal X LOAD WRITE D
(7 )
L H L L X External X LOAD READ Q
(7 )
LX X HValidInternal LOAD WRITE /
BURST WRITE
BURST WRITE
(Advance burst counter)
(2 )
D
(7 )
L X X H X Internal LOAD READ /
BURST READ
BURST READ
(Advance burst counter)
(2 )
Q
(7 )
L X H L X X X DESELECT or STOP
(3 )
HIZ
L X X H X X DESELECT / NOOP NOOP HIZ
H X X X X X X SUSPEND
(4 )
Previous Value
5282 tbl 08
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1 )
11100100
5282 tbl 10
OPERATION R/W
BW
1
BW
2
BW
3
(3)
BW
4
(3 )
READ HXXXX
WRITE ALL BYTES LLLLL
WRITE BYTE 1 (I/O[0:7], I/O
P1
)
(2 )
LLHHH
WRITE BYTE 2 (I/O[8:15], I/O
P2
)
(2)
LHLHH
WRITE BYTE 3 (I/O[16:23], I/O
P3
)
(2,3)
LHHLH
WRITE BYTE 4 (I/O[24:31], I/O
P4
)
(2,3)
LHHHL
NO WRITE LHHHH
5282 tbl 09
