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IDT71V3557SA85BQGI8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
13
Read Operation with Clock Enable Used
(1)
Write Operation with Clock Enable Used
(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Cycle Address R/W ADV/LD
CE
1
(2 )
CEN BWx OE
I/O Comments
nA
0
H L LLXXXAddressA
0
and Control meet setup
n+1 X X X X H X X X Clock n+1 Ignored
n+2 A
1
HL LLXLQ
0
Address A
0
Read out, Load A
1
n+3 X X X XHXLQ
0
Clock Ignored. Data Q
0
is on the bus.
n+4 X X X XHXLQ
0
Clock Ignored. Data Q
0
is on the bus.
n+5 A
2
HL LLXLQ
1
Address A
1
Read out, Load A
2
n+6 A
3
HL LLXLQ
2
Address A
2
Read out, Load A
3
n+7 A
4
HL LLXLQ
3
Address A
3
Read out, Load A
4
5282 tbl 17
Cycle Address R/W ADV/LD
CE
1
(2 )
CEN BWx OE
I/O Comments
nA
0
L L L L L X X Address A
0
and Control meet setup.
n+1 X X X X H X X X Clock n+1 Ignored.
n+2 A
1
L L LLLXD
0
Write data D
0
, Load A
1
.
n+3 X X X X H X X X Clock Ignored.
n+4 X X X X H X X X Clock Ignored.
n+5 A
2
L L LLLXD
1
Write Data D
1
, Load A
2
n+6 A
3
L L LLLXD
2
Write Data D
2
, Load A
3
n+7 A
4
L L LLLXD
3
Write Data D
3
, Load A
4
5282 tbl 18
6.4214
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used
(1)
Write Operation with Chip Enable Used
(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
3. Device outputs are ensured to be in High-Z during device power-up.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle Address R/W ADV/LD
CE
1
(2 )
CEN BWx OE
I/O
(3 )
Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X Z Deselected.
n+2 A
0
H L L L X X Z Address A
0
and Control meet setup.
n+3 X X L H L X L Q
0
Address A
0
read out, Deselected.
n+4 A
1
H L L L X X Z Address A
1
and Control meet setup.
n+5 X X L H L X L Q
1
Address A
1
read out, Deselected.
n+6 X X L H L X X Z Deselected.
n+7 A
2
H L L L X X Z Address A
2
and Control meet setup.
n+8 X X L H L X L Q
2
Address A
2
read out, Deselected.
n+9 X X L H L X X Z Deselected.
5282 tbl 19
Cycle Address R/W ADV/LD
CE
(2 )
CEN BWx OE
I/O Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X Z Deselected.
n+2 A
0
L L L L L X Z Address A
0
and Control meet setup
n+3 X X L H L X X D
0
Data D
0
Write In, Deselected.
n+4 A
1
L L L L L X Z Address A
1
and Control meet setup
n+5 X X L H L X X D
1
Data D
1
Write In, Deselected.
n+6 X X L H L X X Z Deselected.
n+7 A
2
L L L L L X Z Address A
2
and Control meet setup
n+8 X X L H L X X D
2
Data D
2
Write In, Deselected.
n+9 X X L H L X X Z Deselected.
5282 tbl 20
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
15
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(VDD = 3.3V +/-5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test Loads
AC Test Conditions
(VDDQ = 3.3V)
DC Electrical Characterics Over the Operating
Temperature and Supply Voltage Range
(1)
(VDD = 3.3V +/-5%)
NOTE:
1. The LBO, JTAG and ZZ pins will be internally pulled to VDD and ZZ will be internally pulled to VSS if it is not actively driven in the application.
NOTES:
1. All values are maximum guaranteed values.
2. At f = f
MAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
V
DDQ
/
2
50Ω
I/O
Z
0
=50Ω
5282 drw 04
,
1
2
3
4
20 30 50 100 200
ΔtCD
(Typical, ns)
Capacitance (pF)
80
5
6
5282 drw 05
,
Symbol Parameter Test Conditions Min. Max. Unit
|I
LI
| Input Leakage Current V
DD
= Max., V
IN
= 0V to V
DD
___
5µA
|I
LI
|
LBO, JTAG and ZZ Input Leakage Current
(1 )
V
DD
= Max., V
IN
= 0V to V
DD
___
30 µA
|I
LO
| Output Leakage Current V
OUT
= 0V to V
CC
___
5µA
V
OL
Output Low Voltage I
OL
= +8mA, V
DD
= Min.
___
0.4 V
V
OH
Output High Voltage I
OH
= -8mA, V
DD
= Min. 2.4
___
V
5282 tbl 21
Symbol Parameter Test Conditions
7.5ns 8ns 8.5ns
UnitCom'l Only Com'l Ind Com'l Ind
I
DD
Operating Power
Supply Current
Device Selected, Outputs Open,
ADV/LD = X, V
DD
= Max.,
V
IN
> V
IH
or < V
IL
, f = f
MAX
(2)
275 250 260 225 235 mA
I
SB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open,
V
DD
= Max., V
IN
> V
HD
or < V
LD
,
f = 0
(2,3)
40 40 45 40 45 mA
I
SB2
Clock Running Power
Supply Current
Device Deselected, Outputs Open,
V
DD
= Max., V
IN
> V
HD
or < V
LD
,
f = f
MAX
(2,3)
105 100 110 95 105 mA
I
SB3
Idle Power
Supply Current
Device Selected, Outputs Open,
CEN >
V
IH
, V
DD
= Max.,
V
IN
> V
HD
or < V
LD
, f = f
MAX
(2,3)
40 40 45 40 45 mA
5282 tbl 22
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
0 to 3V
2ns
1.5V
1.5V
Figure 1
5282 tbl 23
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IDT71V3557SA85BQGI8

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Description:
IC SRAM 4.5M PARALLEL 165CABGA
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