LTC1709EG-7#PBF Datasheet LTC1709EG-7#TRPBF, LTC1709EG-7#PBF | P10-P12

LTC1709-7

OPERATIO

(Refer to Functional Diagram)

Main Control Loop

The LTC1709-7 uses a constant frequency, current mode

step-down architecture with the two output stages oper-

ating 180 degrees out of phase. During normal operation,

each top MOSFET is turned on when the clock for that

channel sets the RS latch, and turned off when the main

current comparator, I

, resets the RS latch. The peak

inductor current at which I

resets the RS latch is con-

trolled by the voltage on the I

pin, which is the output of

error amplifier EA. The EAIN pin receives the voltage

feedback signal, which is compared to the internal refer-

ence voltage by the EA. When the load current increases,

it causes a slight decrease in V

EAIN

relative to the 0.8V

reference, which in turn causes the I

voltage to increase

until the average inductor current matches the new load

current. After the top MOSFET has turned off, the bottom

MOSFET is turned on until either the inductor current

starts to reverse, as indicated by current comparator I

, or

the beginning of the next cycle.

The top MOSFET drivers are biased from floating boot-

strap capacitor C

, which normally is recharged during

each off cycle through an external diode when the top

MOSFET turns off. As V

decreases to a voltage close to

OUT

, the loop may enter dropout and attempt to turn on

the top MOSFET continuously. The dropout detector de-

tects this and forces the top MOSFET off for about 500ns

every tenth cycle to allow C

to recharge.

The main control loop is shut down by pulling the RUN/

SS pin low. Releasing RUN/SS allows an internal 1.2µA

current source to charge soft-start capacitor C

. When

reaches 1.5V, the main control loop is enabled with

the I

voltage clamped at approximately 30% of its

maximum value. As C

continues to charge, the I

voltage is gradually released allowing normal, full-current

operation.

Low Current Operation

The FCB pin is a multifunction pin providing two func-

tions: 1) to provide regulation for a secondary winding by

temporarily forcing continuous PWM operation on

both controllers; and 2) select between

two

modes of low

current operation. When the FCB pin voltage is below

0.80V, the controller forces continuous PWM current

mode operation. In this mode, the top and bottom

MOSFETs are alternately turned on to maintain the output

voltage independent of direction of inductor current.

When the FCB pin is below V

INTVCC

␣ –␣ 2V but greater than

0.80V, the controller enters Burst Mode operation. Burst

Mode operation sets a minimum output current level

before inhibiting the top switch and turns off the synchro-

nous MOSFET(s) when the inductor current goes nega-

tive. This combination of requirements will, at low currents,

force the I

pin below a voltage threshold that will

temporarily inhibit turn-on of both output MOSFETs until

the output voltage drops. There is 60mV of hysteresis in

the burst comparator B tied to the I

pin. This hysteresis

produces output signals to the MOSFETs that turn them

on for several cycles, followed by a variable “sleep”

interval depending upon the load current. The resultant

output voltage ripple is held to a very small value by

having the hysteretic comparator after the error amplifier

gain block.

Constant Frequency Operation

When the FCB pin is tied to INTV

, Burst Mode operation

is disabled and a forced minimum peak output current

requirement is removed. This provides constant frequency,

discontinuous (preventing reverse inductor current) cur-

rent operation over the widest possible output current

range. This constant frequency operation is not as efficient

as Burst Mode operation, but does provide a lower noise,

constant frequency operating mode down to approxi-

mately 1% of designed maximum output current.

Continuous Current (PWM) Operation

Tying the FCB pin to ground will force continuous current

operation. This is the least efficient operating mode, but

may be desirable in certain applications. The output can

source or sink current in this mode. When sinking current

while in forced continuous operation, current will be

forced back into the main power supply potentially boost-

ing the input supply to dangerous voltage levels—

BEWARE!

LTC1709-7

OPERATIO

(Refer to Functional Diagram)

Frequency Synchronization

The phase-locked loop allows the internal oscillator to be

synchronized to an external source via the PLLIN pin. The

output of the phase detector at the PLLFLTR pin is also the

DC frequency control input of the oscillator that operates

over a 140kHz to 310kHz range corresponding to a DC

voltage input from 0V to 2.4V. When locked, the PLL aligns

the turn on of the top MOSFET to the rising edge of the

synchronizing signal. When PLLIN is left open, the PLLFLTR

pin goes low, forcing the oscillator to minimum frequency.

Input capacitance ESR requirements and efficiency losses

are substantially reduced because the peak current drawn

from the input capacitor is effectively divided by two and

power loss is proportional to the RMS current squared. A

two stage, single output voltage implementation can

reduce input path power loss by 75% and radically reduce

the required RMS current rating of the input capacitor(s).

INTV

/EXTV

Power

Power for the top and bottom MOSFET drivers and most

of the IC circuitry is derived from INTV

. When the

EXTV

pin is left open, an internal 5V low dropout

regulator supplies INTV

power. If the EXTV

pin is

taken above 4.7V, the 5V regulator is turned off and an

internal switch is turned on connecting EXTV

to INTV

This allows the INTV

power to be derived from a high

efficiency external source such as the output of the regu-

lator itself or a secondary winding, as described in the

Applications Information section. An external Schottky

diode can be used to minimize the voltage drop from

EXTV

to INTV

in applications requiring greater than

the specified INTV

current.

Voltages up to 7V can be

applied to EXTV

for additional gate drive capability.

Differential Amplifier

This amplifier provides true differential output voltage

sensing. Sensing both V

OUT

and V

OUT

–

benefits regula-

tion in high current applications and/or applications

having electrical interconnection losses. The amplifier is

not capable of sinking current and therefore must be

resistively loaded to do so.

Output Overvoltage Protection

An overvoltage comparator, OV, guards against transient

overshoots (>7.5%) as well as other more serious condi-

tions that may overvoltage the output. In this case, the top

MOSFET is turned off and the bottom MOSFET is turned on

until the overvoltage condition is cleared.

Power Good (PGOOD)

The PGOOD pin is connected to the drain of an internal

MOSFET. The MOSFET turns on when the output voltage

is not within ±7.5% of its nominal output level as deter-

mined by the feedback divider. When the output is within

±7.5% of its nominal value, the MOSFET is turned off

within 10µs and the PGOOD pin should be pulled up by an

external resistor to a source of up to 7V.

Short-Circuit Detection

The RUN/SS capacitor is used initially to limit the inrush

current from the input power source. Once the control-

lers have been given time, as determined by the capacitor

on the RUN/SS pin, to charge up the output capacitors

and provide full-load current, the RUN/SS capacitor is

then used as a short-circuit timeout circuit. If the output

voltage falls to less than 70% of its nominal output

voltage the RUN/SS capacitor begins discharging as-

suming that the output is in a severe overcurrent and/or

short-circuit condition. If the condition lasts for a long

enough period as determined by the size of the RUN/SS

capacitor, the controller will be shut down until the

RUN/SS pin voltage is recycled. This built-in latchoff can

be overidden by providing a current >5µA at a compli-

ance of 5V to the RUN/SS pin. This current shortens the

soft-start period but also prevents net discharge of the

RUN/SS capacitor during a severe overcurrent and/or

short-circuit condition. Foldback current limiting is acti-

vated when the output voltage falls below 70% of its

nominal level whether or not the short-circuit latchoff

circuit is enabled.

LTC1709-7

APPLICATIO S I FOR ATIO

WUU

The basic LTC1709-7 application circuit is shown in

Figure␣ 1 on the first page. External component selection

begins with the selection of the inductor(s) based on

ripple current requirements and continues with the

SENSE1, 2

resistor selection using the calculated peak

inductor current and/or maximum current limit. Next, the

power MOSFETs and D1 and D2 are selected. The oper-

ating frequency and the inductor are chosen based mainly

on the amount of ripple current. Finally, C

is selected for

its ability to handle the input ripple current (that

PolyPhase

operation minimizes) and C

OUT

is chosen

with low enough ESR to meet the output ripple voltage

and load step specifications (also minimized with

PolyPhase). Current mode architecture provides inherent

current sharing between output stages. The circuit shown

in Figure␣ 1 can be configured for operation up to an input

voltage of 28V (limited by the external MOSFETs). Current

mode control allows the ability to connect the two output

stages to two different input power supply rails. A heavy

output load can take some power from each input supply

according to the selection of the R

SENSE

resistors.

SENSE

Selection For Output Current

SENSE1, 2

are chosen based on the required peak output

current. The LTC1709-7 current comparator has a maxi-

mum threshold of 75mV/R

SENSE

and an input common

mode range of SGND to 1.1(INTV

). The current com-

parator threshold sets the peak inductor current, yielding

a maximum average output current I

MAX

equal to the peak

value less half the peak-to-peak ripple current, ∆I

Assuming a common input power source for each output

stage and allowing a margin for variations in the

LTC1709-7 and external component values yields:

SENSE

= 2(50mV/I

MAX

)

Operating Frequency

The LTC1709-7 uses a constant frequency, phase-lock-

able architecture with the frequency determined by an

internal capacitor. This capacitor is charged by a fixed

current plus an additional current which is proportional

to the voltage applied to the PLLFLTR pin. Refer to Phase-

Locked Loop and Frequency Synchronization for addi-

tional information.

A graph for the voltage applied to the PLLFLTR pin vs

frequency is given in Figure␣ 2. As the operating frequency

is increased the gate charge losses will be higher, reducing

efficiency (see Efficiency Considerations). The maximum

switching frequency is approximately 310kHz.

Figure 2. Operating Frequency vs V

PLLFLTR

PolyPhase is a registered trademark of Linear Technology Corporation.

OPERATING FREQUENCY (kHz)

120 170 220 270 320

PLLFLTR PIN VOLTAGE (V)

17097 F02

2.5

2.0

1.5

1.0

0.5

Inductor Value Calculation and Output Ripple Current

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because

MOSFET gate charge and transition losses increase di-

rectly with frequency. In addition to this basic tradeoff, the

effect of inductor value on ripple current and low current

operation must also be considered. The PolyPhase ap-

proach reduces both input and output ripple currents

while optimizing individual output stages to run at a lower

fundamental frequency, enhancing efficiency.

The inductor value has a direct effect on ripple current.

The inductor ripple current ∆I

per individual section, N,

decreases with higher inductance or frequency and

increases with higher V

or V

OUT

∆I

OUT OUT

=−













where f is the individual output stage operating frequency.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

LTC1709EG-7#PBF

Mfr. #:

Buy LTC1709EG-7#PBF

Manufacturer:

Analog Devices / Linear Technology

Description:

Switching Voltage Regulators Hi Pwr Polyphase Dc/DC Controller

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

LTC1709EG-7#PBF

LTC1709EG-7#PBF

Products related to this Datasheet