20
LTC1709-7
If the external frequency (f
PLLIN
) is greater than the oscil-
lator frequency f
0SC
, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency
is less than f
0SC
, current is sunk continuously, pulling
down the PLLFLTR pin. If the external and internal fre-
quencies are the same but exhibit a phase difference, the
current sources turn on for an amount of time correspond-
ing to the phase difference. Thus the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point the phase comparator output is
open and the filter capacitor C
LP
holds the voltage. The
LTC1709-7 PLLIN pin must be driven from a low imped-
ance source such as a logic gate located close to the pin.
The loop filter components (C
LP
, R
LP
) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C
LP
and R
LP
determine how fast the loop
acquires lock. Typically R
LP
=10k and C
LP
is 0.01µF to
0.1µF.
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN)
, is the smallest time duration
that the LTC1709-7 is capable of turning on the top
MOSFET. It is determined by internal timing delays and the
gate charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
t
V
Vf
ON MIN
OUT
IN
()
<
()
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1709-7 will begin to skip
cycles resulting in variable frequency operation. The out-
put voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.
The minimum on-time for the LTC1709-7 is generally less
than 200ns. However, as the peak sense voltage de-
creases, the minimum on-time gradually increases. This is
of particular concern in forced continuous applications
with low ripple current at light loads. If the duty cycle drops
below the minimum on-time limit in this situation, a
significant amount of cycle skipping can occur with corre-
spondingly larger ripple current and voltage ripple.
If an application can operate close to the minimum
on-time limit, an inductor must be chosen that has a low
enough inductance to provide sufficient ripple amplitude
to meet the minimum on-time requirement.
As a general
rule, keep the inductor ripple current of each phase equal
to or greater than 15% of I
OUT(MAX)
at V
IN(MAX)
.
FCB Pin Operation
The FCB pin can be used to regulate a secondary winding
or as a logic level input. Continuous operation is forced
when the FCB pin drops below 0.8V. During continuous
mode, current flows continuously in the transformer pri-
mary. The secondary winding(s) supply current only when
the bottom, synchronous switch is on. When primary load
currents are low and/or the V
IN
/V
OUT
ratio is low, the
synchronous switch may not be on for a sufficient amount
of time to transfer power from the output capacitor to the
secondary load. Forced continuous operation will support
secondary windings providing there is sufficient synchro-
nous switch duty factor. Thus, the FCB input pin removes
the requirement that power must be drawn from the
inductor primary in order to extract power from the
auxiliary winding(s). With the loop in continuous mode,
the auxiliary output(s) may nominally be loaded without
regard to the primary output load.
APPLICATIO S I FOR ATIO
WUU
U
Figure 7. Phase-Locked Loop Block Diagram
EXTERNAL
OSC
2.4V
R
LP
10k
C
LP
OSC
DIGITAL
PHASE/
FREQUENCY
DETECTOR
PHASE
DETECTOR
PLLIN
1709 F07
PLLFLTR
50k
