8
LTC1709-7
PI FU CTIO S
UUU
PGOOD (Pin 23): Open-Drain Logic Output. PGOOD is
pulled to ground when the voltage on the EAIN pin is not
within ±7.5% of its set point.
TG2, TG1 (Pins 24, 35): High Current Gate Drives for Top
N-Channel MOSFETS. These are the outputs of floating
drivers with a voltage swing equal to INTV
CC
superim-
posed on the switch node voltage SW.
SW2, SW1 (Pins 25, 34): Switch Node Connections to
Inductors. Voltage swing at these pins is from a Schottky
diode (external) voltage drop below ground to V
IN
.
BOOST2, BOOST1 (Pins 26, 33): Bootstrapped Supplies
to the Topside Floating Drivers. External capacitors are
connected between the BOOST and SW pins, and Schottky
diodes are connected between the BOOST and INTV
CC
pins.
BG2, BG1 (Pins 27, 31): High Current Gate Drives for
Bottom N-Channel MOSFETS. Voltage swing at these pins
is from ground to INTV
CC
.
PGND (Pin 28): Driver Power Ground. Connect to sources
of bottom N-channel MOSFETS and the (–) terminals of
C
IN
.
INTV
CC
(Pin 29): Output of the Internal 5V Linear Low
Dropout Regulator and the EXTV
CC
Switch. The driver and
control circuits are powered from this voltage source.
Decouple to power ground with a 1µF ceramic capacitor
placed directly adjacent to the IC and minimum of 4.7µF
additional tantalum or other low ESR capacitor.
EXTV
CC
(Pin 30): External Power Input to an Internal
Switch. This switch closes and supplies INTV
CC,
bypass-
ing the internal
low dropout regulator whenever EXTV
CC
is
higher than 4.7V. See EXTV
CC
Connection in the Applica-
tions Information section. Do not exceed 7V on this pin
and ensure V
EXTVCC
≤ V
INTVCC
.
V
IN
(Pin 32): Main Supply Pin. Should be closely decoupled
to the IC’s signal ground pin.
NC (Pin 36): Do Not Connect.
PLLFLTR (Pin 5): The phase-locked loop’s lowpass filter
is tied to this pin. Alternatively, this pin can be driven with
an AC or DC voltage source to vary the frequency of the
internal oscillator.
PLLIN (Pin 6): External Synchronization Input to Phase
Detector. This pin is internally terminated to SGND with
50kΩ. The phase-locked loop will force the rising top gate
signal of controller 1 to be synchronized with the rising
edge of the PLLIN signal.
FCB (Pin 7): Forced Continuous Control Input. This input
acts on both output stages and can be used to regulate a
secondary winding. Pulling this pin below 0.8V will force
continuous synchronous operation. Do not leave this pin
floating without a decoupling capacitor.
I
TH
(Pin 8): Error Amplifier Output and Switching Regula-
tor Compensation Point. Both current comparator’s thresh-
olds increase with this control voltage. The normal voltage
range of this pin is from 0V to 2.4V
SGND (Pin 9): Signal Ground. This pin is common to both
controllers. Route separately to the PGND pin.
V
DIFFOUT
(Pin 10): Output of a Differential Amplifier. This
pin provides true remote output voltage sensing. V
DIFFOUT
normally drives an external resistive divider that sets the
output voltage.
V
OS
–
, V
OS
+
(Pins 11, 12): Inputs to an Operational Ampli-
fier. Internal precision resistors configure it as a differen-
tial amplifier whose output is V
DIFFOUT
.
ATTENOUT (Pin 15): Voltage Feedback Signal Resistively
Divided According to the VID Programming Code.
ATTENIN (Pin 16): The Input to the VID Controlled Resis-
tive Divider.
VID0–VID4 (Pins 17,18, 19, 20, 21): VID Control Logic
Input Pins.
V
BIAS
(Pin 22): Supply Pin for the VID Control Circuit.
