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ISL54005IRTZ-T

P1-P3P4-P6P7-P9P10-P12P13-P15
13
FN6514.2
October 30, 2007
FIGURE 15. THD+N vs OUTPUT POWER FIGURE 16. THD+N vs OUTPUT POWER
FIGURE 17. THD+N vs OUTPUT POWER FIGURE 18. THD+N vs OUTPUT POWER
FIGURE 19. CROSSTALK vs FREQUENCY FIGURE 20. OFF ISOLATION vs FREQUENCY
Typical Performance Curves T
A
= +25°C, Unless Otherwise Specified. (Continued)
THD+N (%)
OUTPUT POWER (W)
0.01
10.0
0.02
0.05
0.10
0.20
0.50
1.00
2.00
5.00
10m 100m20m 30m 40m 50m 70m
V
DD
= 5V
SE
R
L
= 32
f = 1kHz
THD+N (%)
OUTPUT POWER (W)
0.01
10.0
0.02
0.05
0.10
0.20
0.50
1.00
2.00
5.00
10m 200m20m 30m 50m 70m 100m
R
L
= 16
V
DD
= 5V
SE
f = 1kHz
THD+N (%)
OUTPUT POWER (W)
0.01
1.00
0.02
0.05
0.10
0.20
0.50
1.00
2.00
5.00
10m 55m12m 15m 20m 25m 35m 45m
V
DD
= 3.6V
SE
R
L
= 32
f = 1kHz
OUTPUT POWER (W)
THD+N (%)
0.01
10.0
0.02
0.05
0.01
0.20
0.50
1.00
2.00
5.00
10m 100m20m 30m 40m 50m 70m
V
DD
= 3.6V
SE
R
L
= 16
f = 1kHz
CROSSTALK (dB)
FREQUENCY (Hz)
-110
-50
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
20 20k50 100 200 500 1k 2k 5k 10k
INxR TO HPL
INxL TO HPR
V
DD
= 5V
P
O
= 15mW
OFF ISOLATION (dB)
FREQUENCY (Hz)
-160
-80
-155
-150
-145
-140
-135
-130
-125
-120
-115
-110
-105
-100
-95
-90
-85
20 20k50 100 200 500 1k 2k 5k 10k
HPR AND HPL
BTL
ISL54003, ISL54005, ISL54006
14
FN6514.2
October 30, 2007
FIGURE 21. PSRR vs FREQUENCY
FIGURE 22. PSRR vs FREQUENCY
FIGURE 23. POWER DISSIPATION vs OUTPUT POWER FIGURE 24. POWER DISSIPATION vs OUTPUT POWER
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
PROCESS:
Submicron CMOS
Typical Performance Curves T
A
= +25°C, Unless Otherwise Specified. (Continued)
PSRR (dB)
FREQUENCY (Hz)
-70
-66
-62
-58
-54
-50
-46
-42
-38
-34
-30
-26
-22
10 20k20 50 100 200 500 1k 2k 5k 10k
V
DD
= 5V
BTL
V
RIPPLE
= 200mV
P-P
PSRR (dB)
FREQUENCY (Hz)
-90
-20
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
10 20k20 50 100 200 500 1k 2k 5k 10k
V
DD
= 5V
V
RIPPLE
= 200mV
P-P
SE
HPR
HPL
P
OUT
(mW)
POWER DISSIPATION (mW)
0
100
200
300
400
500
600
700
0 250 500 750 1000
V
DD
= 5V
BTL
R
L
= 8W
P
OUT
(mW)
POWER DISSIPATION (mW)
0
50
100
150
200
250
300
350
400
0 100 200 300 400
500
V
DD
= 3.6V
BTL
R
L
= 8W
ISL54003, ISL54005, ISL54006
15
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6514.2
October 30, 2007
ISL54003, ISL54005, ISL54006
Thin Quad Flat No-Lead Plastic Package
(TQFN)
Thin Micro Lead FramePlastic Package
(TMLFP)
L20.4x4A
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220WGGD-1 ISSUE I)
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.70 0.75 0.80 -
A1 - 0.02 0.05 -
A2 - 0.55 0.80 9
A3 0.20 REF 9
b 0.18 0.25 0.30 5, 8
D 4.00 BSC -
D1 3.75 BSC 9
D2 1.95 2.10 2.25 7, 8
E 4.00 BSC -
E1 3.75 BSC 9
E2 1.95 2.10 2.25 7, 8
e 0.50 BSC -
k0.20 - - -
L 0.35 0.60 0.75 8
N202
Nd 5 3
Ne 5 3
P- -0.609
--129
Rev. 0 11/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & are present when
Anvil singulation method is used and not present for saw
singulation.
P1-P3P4-P6P7-P9P10-P12P13-P15

ISL54005IRTZ-T

Mfr. #:
Buy ISL54005IRTZ-T
Manufacturer:
Renesas / Intersil
Description:
Audio Amplifiers MONO 1 1 W/INTEGRTD SUBSYSTEM W/STEREO
Lifecycle:
New from this manufacturer.
Delivery:
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