13
FN2967.4
October 2, 2015
82C37A
External EOP Operation
The EOP pin is a bidirectional, open drain pin which may be
driven by external signals to terminate DMA operation.
Because EOP
is an open drain pin an external pull-up
resistor to V
CC
is required. The value of the external pull-up
resistor used should guarantee a rise time of less than
125ns. It is important to note that the 82C37A will not accept
external EOP
signals when it is in a SI (Idle) state. The
controller must be active to latch EXT EOP
. Once latched,
the EXT EOP
will be acted upon during the next S2 state,
unless the 82C37A enters an idle state first. In the latter
case, the latched EOP
is cleared. External EOP pulses
occurring between active DMA transfers in demand mode
will not be recognized, since the 82C37A is in an SI state.
Application Information
Figure 6 shows an application for a DMA system utilizing the
82C37A DMA controller and the 80C88 Microprocessor. In
this application, the 82C37A DMA controller is used to
improve system performance by allowing an I/O device to
transfer data directly to or from system memory.
Components
The system clock is generated by the 82C84A clock driver
and is inverted to meet the clock high and low times required
by the 82C37A DMA controller. The four OR gates are used
to support the 80C88 Microprocessor in minimum mode by
producing the control signals used by the processor to
access memory or I/O. A decoder is used to generate chip
select for the DMA controller and memory. The most
significant bits of the address are output on the address/data
bus. Therefore, the 82C82 octal latch is used to demultiplex
the address. Hold Acknowledge (HLDA) and Address
Enable (AEN) are “ORed” together to insure that the DMA
controller does not have bus contention with the
microprocessor.
Operation
A DMA request (DREQ) is generated by the I/O device. After
receiving the DMA request, the DMA controller will issue a
Hold request (HRQ) to the processor. The system busses
are not released to the DMA controller until a Hold
Acknowledge signal is returned to the DMA controller from
the 80C88 processor. After the Hold Acknowledge has been
CHANNEL REGISTER OPERATION
SIGNALS FIRST/LAST
FLIP-FLOP
STATE
DATA BUS
DB0-DB7CS
IOR IOW A3 A2 A1 A0
0 Base and Current Address Write 0100000 0 A0-A7
0100000 1 A8-A15
Current Address Read 0010000 0 A0-A7
0010000 1 A8-A15
Base and Current Word
Count
Write 0100001 0 W0-W7
0100001 1 W8-W15
Current Word Count Read 0010001 0 W0-W7
0010001 1 W8-W15
1 Base and Current Address Write 0100010 0 A0-A7
0100010 1 A8-A15
Current Address Read 0010010 0 A0-A7
0010010 1 A8-A15
Base and Current Word
Count
Write 0100011 0 W0-W7
0100011 1 W8-W15
Current Word Count Read 0010011 0 W0-W7
0010011 1 W8-W15
2 Base and Current Address Write 0100100 0 A0-A7
0100100 1 A8-A15
Current Address Read 0010100 0 A0-A7
0010100 1 A8-A15
Base and Current Word
Count
Write 0100101 0 W0-W7
0100101 1 W8-W15
Current Word Count Read 0010101 0 W0-W7
0010101 1 W8-W15
3 Base and Current Address Write 0100110 0 A0-A7
0100110 1 A8-A15
Current Address Read 00101100 A0-A7
00101101 A8-A15
Base and Current Word
Count
Write 01001110 W0-W7
01001111 W8-W15
Current Word Count Read 00101110 W0-W7
00101111 W8-W15
FIGURE 5. WORD COUNT AND ADDRESS REGISTER COMMAND CODES
