7
FN2967.4
October 2, 2015
82C37A
system busses and enter the active cycle. The active cycle is
composed of several internal states, depending on what
options have been selected and what type of operation has
been requested.
The 82C37A can assume seven separate states, each
composed of one full clock period. State I (SI) is the idle
state. It is entered when the 82C37A has no valid DMA
requests pending, at the end of a transfer sequence, or
when a Reset or Master Clear has occurred. While in SI, the
DMA controller is inactive but may be in the Program
Condition (being programmed by the processor).
State 0 (S0) is the first state of a DMA service. The 82C37A
has requested a hold but the processor has not yet returned
an acknowledge. The 82C37A may still be programmed until
it has received HLDA from the CPU. An acknowledge from
the CPU will signal the DMA transfer may begin. S1, S2, S3,
and S4 are the working state of the DMA service. If more
time is needed to complete a transfer than is available with
normal timing, wait states (SW) can be inserted between S3
and S4 in normal transfers by the use of the Ready line on
the 82C37A. For compressed transfers, wait states can be
inserted between S2 and S4. See timing Figures 14 and 15.
Note that the data is transferred directly from the I/O device
to memory (or vice versa) with IOR
and MEMW (or MEMR
and IOW
) being active at the same time. The data is not read
into or driven out of the 82C37A in I/O-to-memory or
memory-to-I/O DMA transfers.
Memory-to-memory transfers require a read-from and a write-
to memory to complete each transfer. The states, which
resemble the normal working states, use two-digit numbers
for identification. Eight states are required for a single transfer.
The first four states (S11, S12, S13, S14) are used for the
read-from-memory half and the last four state (S21, S22, S23,
S24) for the write-to-memory half of the transfer.
Idle Cycle
When no channel is requesting service, the 82C37A will
enter the idle cycle and perform “SI” states. In this cycle, the
82C37A will sample the DREQ lines on the falling edge of
every clock cycle to determine if any channel is requesting a
DMA service.
Note that for standby operation where the clock has been
stopped, DMA requests will be ignored. The device will
respond to CS
(chip select), in case of an attempt by the
microprocessor to write or read the internal registers of the
82C37A. When CS
is low and HLDA is low, the 82C37A
enters the Program Condition. The CPU can now establish,
change or inspect the internal definition of the part by
reading from or writing to the internal registers.
The 82C37A may be programmed with the clock stopped,
provided that HLDA is low and at least one rising clock edge
has occurred after HLDA was driven low, so the controller is in
an SI state. Address lines A0-A3 are inputs to the device and
select which registers will be read or written. The IOR and IOW
lines are used to select and time the read or write operations.
Due to the number and size of the internal registers, an internal
flip-flop called the First/Last Flip-Flop is used to generate an
additional bit of address. The bit is used to determine the upper
or lower byte of the 16-bit Address and Work Count registers.
The flip-flop is reset by Master Clear or RESET. Separate
software commands can also set or reset this flip-flop.
Special software commands can be executed by the
82C37A in the Program Condition. These commands are
decoded as sets of addresses with CS
, IOR, and IOW. The
commands do not make use of the data bus. Instructions
include Set and Clear First/Last Flip-Flop, Master Clear,
Clear Mode Register Counter, and Clear Mask Register.
Active Cycle
When the 82C37A is in the Idle cycle, and a software
request or an unmasked channel requests a DMA service,
the device will issue HRQ to the microprocessor and enter
the Active cycle. It is in this cycle that the DMA service will
take place, in one of four modes:
Single Transfer Mode - In Single Transfer mode, the device
is programmed to make one transfer only. The word count
will be decremented and the address decremented or
incremented following each transfer. When the word count
“rolls over” from zero to FFFFH, a terminal count bit in the
status register is set, an EOP
pulse is generated, and the
channel will autoinitialize if this option has been selected. If
not programmed to autoinitialize, the mask bit will be set,
along with the TC bit and EOP
pulse.
DREQ must be held active until DACK becomes active. If
DREQ is held active throughout the single transfer, HRQ will
go inactive and release the bus to the system. It will again go
active and, upon receipt of a new HLDA, another single
transfer will be performed, unless a higher priority channel
takes over. In 8080A, 8085A, 80C88, or 80C86 systems, this
will ensure one full machine cycle execution between DMA
transfers. Details of timing between the 82C37A and other
bus control protocols will depend upon the characteristics of
the microprocessor involved.
Block Transfer Mode - In Block Transfer mode, the device
is activated by DREQ or software request and continues
making transfers during the service until a TC, caused by
word count going to FFFFH, or an external End of Process
(EOP
) is encountered. DREQ need only be held active until
DACK becomes active. Again, an Autoinitialization will occur
at the end of the service if the channel has been
programmed for that option.
Demand Transfer Mode - In Demand Transfer mode the
device continues making transfers until a TC or external EOP is
encountered, or until DREQ goes inactive. Thus, transfer may
continue until the I/O device has exhausted its data capacity.
