Features
Single Voltage Operation Read/Write: 2.65V - 3.6V
2.7V - 3.6V Read/Write
Access Time 70 ns
Sector Erase Architecture
One Hundred Twenty-seven 32K Word Main Sectors with Individual Write Lockout
Eight 4K Word Sectors with Individual Write Lockout
Fast Word Program Time 10 µs
Typical Sector Erase Time: 32K Word Sectors 500 ms; 4K Word Sectors 100 ms
Suspend/Resume Feature for Erase and Program
Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
10 mA Active
15 µA Standby
Data Polling and Toggle Bit for End of Program Detection
VPP Pin for Write Protection and Accelerated Program Operations
RESET Input for Device Initialization
Sector Lockdown Support
TSOP Package
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Common Flash Interface (CFI)
Green (Pb/Halide-free) Packaging
1. Description
The AT49BV642D(T) is a 2.7-volt 64-megabit Flash memory organized as 4,194,304
words of 16 bits each. The memory is divided into 135 sectors for erase operations.
The device can be read or reprogrammed off a single 2.7V power supply, making it
ideally suited for in-system programming.
To increase the flexibility of the device, it contains an Erase Suspend and Program
Suspend feature. This feature will put the erase or program on hold for any amount of
time and let the user read data from or program data to any of the remaining sectors.
The end of program or erase is detected by Data Polling or toggle bit.
The VPP pin provides data protection and faster programming times. When the V
PP
input is below 0.4V, the program and erase functions are inhibited. When V
PP
is at
1.65V or above, normal program and erase operations can be performed. With V
PP
at
10.0V, the program (dual-word program command) operation is accelerated.
A six-word command (Enter Single Pulse Program Mode) to remove the requirement
of entering the three-word program sequence is offered to further improve program-
ming time. After entering the six-word code, only single pulses on the write control
lines are required for writing into the device. This mode (Single Pulse Word Program)
is exited by powering down the device, by taking the RESET pin to GND or by a high-
to-low transition on the V
PP
input. Erase, Erase Suspend/Resume, Program Sus-
pend/Resume and Read Reset commands will not work while in this mode; if entered
they will result in data being programmed into the device. It is not recommended that
the six-word code reside in the software of the final product but only exist in external
programming code.
64-megabit
(4M x 16)
3-volt Only
Flash Memory
AT49BV642D
AT49BV642DT
Not
Recommended
for New Design
3631A–FLASH–04/06
2
3631A–FLASH–04/06
AT49BV642D(T)
2. Pin Configurations
2.1 TSOP Top View (Type 1)
Pin Name Pin Function
I/O0 - I/O15 Data Inputs/Outputs
A0 - A21 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
RESET Reset
VPP
Write Protection and Power Supply for Accelerated Program
Operations
VCCQ Output Power Supply
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE
RESET
VPP
NC
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
VCCQ
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
3
3631A–FLASH–04/06
AT49BV642D(T)
3. Device Operation
3.1 Command Sequences
The device powers on in the read mode. Command sequences are used to place the device in
other operating modes such as program and erase. After the completion of a program or an
erase cycle, the device enters the read mode. The command sequences are written by applying
a low pulse on the WE input with CElowandOE high or by applying a low-going pulse on the
CE input with WE low and OE high. The address is latched on the falling edge of the WE or CE
pulse whichever occurs first. Valid data is latched on the rising edge of the WE or the CE pulse,
whichever occurs first. The addresses used in the command sequences are not affected by
entering the command sequences.
3.2 Read
The AT49BV642D(T) is accessed like an EPROM. When CE and OE are low and WE is high,
the data stored at the memory location determined by the address pins are asserted on the out-
puts. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention.
3.3 Reset
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET pin halts the
present device operation and puts the outputs of the device in a high-impedance state. When a
high level is reasserted on the RESET pin, the device returns to read or standby mode, depend-
ing upon the state of the control pins.
3.4 Erase
Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a
logical “1”. The entire memory can be erased by using the Chip Erase command or individual
sectors can be erased by using the Sector Erase command.
3.4.1 Chip Erase
Chip Erase is a six-bus cycle operation. The automatic erase begins on the rising edge of the
last WE pulse. Chip Erase does not alter the data of the protected sectors. After the full chip
erase the device will return back to the read mode. The hardware reset during Chip Erase will
stop the erase but the data will be of unknown state. Any command during Chip Erase except
Erase Suspend will be ignored.
3.4.2 Sector Erase
As an alternative to a full chip erase, the device is organized into multiple sectors that can be
individually erased. The Sector Erase command is a six-bus cycle operation. The sector whose
address is valid at the sixth falling edge of WE will be erased provided the given sector has not
been protected.

AT49BV642DT-70TU

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
NOR Flash 64M FLASH-64M 2.7V TOP BOOT
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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