19
3631A–FLASH–04/06
AT49BV642D(T)
17. Asynchronous Read Cycle Waveform
(1)(2)(3)
Notes: 1. CE may be delayed up to t
ACC
-t
CE
after the address transition without impact on t
ACC
.
2.
OE may be delayed up to t
CE
-t
OE
after the falling edge of CE without impact on t
CE
or by t
ACC
-t
OE
after an address change
without impact on t
ACC
.
3. t
DF
is specified from OE or CE, whichever occurs first (CL = 5 pF).
16. AC Read Characteristics
Symbol Parameter Min Max Units
t
RC
Read Cycle Time 70 ns
t
ACC
Access, Address to Data Valid 70 ns
t
CE
Access, CE to Data Valid 70 ns
t
OE
OE to Data Valid 20 ns
t
DF
CE, OE High to Data Float 25 ns
t
OH
Output Hold from OE, CE or Address, whichever Occurs First 0 ns
t
RO
RESET to Output Delay 100 ns
OUTPUT
VALID
I/O0 - I/O15
HIGH Z
RESET
OE
t
OE
t
CE
ADDRESS VALID
t
DF
t
OH
t
ACC
t
RO
CE
A0 - A21
t
RC
20
3631A–FLASH–04/06
AT49BV642D(T)
19. AC Word Load Waveforms
19.1 WE Controlled
19.2 CE Controlled
18. AC Word Load Characteristics
Symbol Parameter Min Max Units
t
AS
,t
OES
Address, OE Setup Time 0 ns
t
AH
Address Hold Time 25 ns
t
CS
Chip Select Setup Time 0 ns
t
CH
Chip Select Hold Time 0 ns
t
WP
Write Pulse Width (WE or CE) 25 ns
t
WPH
Write Pulse Width High 15 ns
t
DS
Data Setup Time 25 ns
t
DH
,t
OEH
Data, OE Hold Time 0 ns
21
3631A–FLASH–04/06
AT49BV642D(T)
21. Program Cycle Waveforms
22. Sector or Chip Erase Cycle Waveforms
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.
(See note 3 under “Command Definition Table” on page 11.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
20. Program Cycle Characteristics
Symbol Parameter Min Typ Max Units
t
BP
Word Programming Time 10 120 µs
t
BPD
Word Programming Time in Dual Programming Mode 5 60 µs
t
AS
Address Setup Time 0 ns
t
AH
Address Hold Time 25 ns
t
DS
Data Setup Time 25 ns
t
DH
Data Hold Time 0 ns
t
WP
Write Pulse Width 25 ns
t
WPH
Write Pulse Width High 15 ns
t
WC
Write Cycle Time 70 ns
t
RP
Reset Pulse Width 500 ns
t
EC
Chip Erase Cycle Time 64 seconds
t
SEC1
Sector Erase Cycle Time (4K Word Sectors) 0.1 2.0 seconds
t
SEC2
Sector Erase Cycle Time (32K Word Sectors) 0.5 6.0 seconds
t
ES
Erase Suspend Time 15 µs
t
PS
Program Suspend Time 10 µs
OE
PROGRAM CYCLE
INPUT
DA TA
ADDRESS
A0
55
555 555
AA
AAA
t
BP
t
WPH
t
WP
CE
WE
A0 - A21
DA TA
t
AS
t
AH
t
DH
t
DS
555
AA
t
WC
OE
(1)
AA
80
Note 3
55 55
555
555
Note 2
AA
WORD 0
WORD 1 WORD 2
WORD 3
WORD 4
WORD 5
AAA AAA
t
WPH
t
WP
CE
WE
A0-A21
DA TA
t
AS
t
AH
t
EC
t
DH
t
DS
555
t
WC

AT49BV642DT-70TU

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
NOR Flash 64M FLASH-64M 2.7V TOP BOOT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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