Z86C83/C84/E83
CMOS Z8
®
MCU Zilog
8-22 P R E L I M I N A R Y DS97DZ80700
PIN FUNCTIONS
EPROM Programming Mode (E83 Only)
D7-D0. Data Bus. The data can be read from or written to
the EPROM through the data bus.
Clock. Address Clock. This pin is a clock input. The inter-
nal address counter increases by one with one clock sig-
nal.
Clear. Clear. (active High). This pin resets the internal ad-
dress counter at the High Level.
V
CC.
Power Supply. This pin must supply 5V during the
EPROM Read Mode and 6V during other modes.
/CE. Chip Enable (active Low). This pin is active during
EPROM Read, Program, and Program Verify Modes.
/OE. Output Enable (active Low). This pin drives the direc-
tion of the Data Bus. When this pin is Low, the Data Bus is
output, when High, the Data Bus is input.
EPM. EPROM Program Mode. This pin controls the differ-
ent EPROM Program Mode by applying different voltages.
V
PP.
Program Voltage. This pin supplies the program volt-
age.
/PGM. Program Mode (active Low). When this pin is Low,
the data is programmed to the EPROM through the Data
Bus.
Application Precaution
The production test-mode environment may be enabled
accidentally during normal operation if excessive noise
surges above V
cc
occur on the /RESET pin.
Processor operation of Z8
OTP devices may be affected
by excessive noise surges on the VPP, /EPM, /OE pins
while the microcontroller is in Standard Mode.
Recommendations for dampening voltage surges in both
test and OTP mode include the following:
■ Using a clamping diode to /RESET, VPP, /EPM, /OE
■ Adding a capacitor to the affected pin
Z86C83, Z86C84, and Standard Mode Z86E83
XTAL1. Crystal 1 (time-based input). This pin connects a
parallel-resonant crystal, ceramic resonator, LC network
or an external single-phase clock to the on-chip oscillator
input.
XTAL2. Crystal 2 (time-based output). This pin connects a
parallel-resonant crystal, ceramic resonator, LC network to
the on-chip oscillator output.
Port 0 P00-P06 (P03-P06 is not available on the Z86C84).
Port 0 is a 7-bit, bidirectional, CMOS-compatible I/O port.
These seven I/O lines can be nibble programmable as
P00-P03 input/output and P04-P06 input/output, separate-
ly (Figure 10). All input buffers are Schmitt-triggered and
output drivers are push-pull.
Port 0 Auto Latch. (P03-P06 has the Auto Latches per-
manently enabled). The Auto Latch provides valid CMOS
Levels when P03-P06 are selected as inputs and not ex-
ternally driven. It is impossible to determine if a non-driven
input is 1 or 0, however; the Auto Latch will sense the input
condition and drive a valid CMOS level, thereby eliminat-
ing a floating mode that could cause excessive current.
