Z86C83/C84/E83
Zilog CMOS Z8
®
MCU
DS97DZ80700 P R E L I M I N A R Y 8-39
1
Power-On Reset (POR). A timer circuit clocked by a ded-
icated on-board RC oscillator or by the XTAL oscillator is
used for the POR timer function. The POR time allows V
CC
and the oscillator circuit to stabilize before instruction exe-
cution begins. The POR timer circuit is a one-shot timer
triggered by one of three conditions:
■ Power Fail to Power OK Status
■ Stop-Mode Recovery (If D5 of SMR Register = 1)
■ WDT Time-Out (Including from STOP Mode)
The POR time is T
POR
minimum. Bit 5 of the STOP Mode
Register determines whether the POR timer is bypassed
after Stop-Mode Recovery (typical for external clock and
LC oscillators with fast start up time).
HALT. Turns off the internal CPU clock but not the XTAL
oscillation. The counter/timers and external interrupts
IRQ0, IRQ1, and IRQ2 remain active. The device is recov-
ered by interrupts, either externally or internally generated
(a POR or a WDT time-out). An interrupt request must be
executed (enabled) to exit HALT Mode. After the interrupt
service routine, the program continues from the instruction
after the HALT. In case of a POR or a WDT time-out, pro-
gram execution will restart at address 000CH.
STOP. This instruction turns off the internal clock and ex-
ternal crystal oscillation and reduces the standby current
to 10 µA (typical) or less. The STOP Mode is terminated by
a reset of either WDT time-out, POR, or Stop-Mode Re-
covery. This causes the processor to restart the applica-
tion program at address 000CH.
Figure 33. Gain Control on DAC
3.5
3.05
2.6
2.15
2% accuracy
1.7
1.26
.8VDLO
0 80H
FFH
3.5V
VDHI
1/4X
1/2X
1X
DAC Output in Volts
2.15
DAC Data Register Value
Notes:
Vcc = 5.0V ±10%
VDHI = 3.5V
VDLO = 0.8V
