Z86C83/C84/E83
Zilog CMOS Z8
®
MCU
DS97DZ80700 P R E L I M I N A R Y 8-43
1
WDT Time Select (D1, D0). Selects the WDT time-out pe-
riod. It is configured as shown in Table 15.
WDT During HALT (D2). This bit determines whether or
not the WDT is active during HALT Mode. A "1" indicates
active during HALT. The default is "1".
Note: If WDT is permanently selected (always ON mode),
the WDT will continue to run even if set not to run in STOP
or HALT Mode.
WDT During STOP (D3). This bit determines whether or
not the WDT is active during STOP Mode. Since XTAL
clock is stopped during STOP Mode, unless as specified
below, the on-board RC has to be selected as the clock
source to the POR counter. A "1" indicates active during
STOP. The default is "1". If bits D3 and D4 are both set to
"1", the WDT only, is driven by the external clock during
STOP Mode.
Notes:
1. If WDT is permanently selected (always ON mode)
using internal on-board RC oscillator, the WDT will
continue to run even if set not to run in STOP or HALT
Mode.
2. WDT instructions affect the Z (Zero), S (Sign), and V
(Overflow) flags.
On-Board, Power-On-Reset RC or External XTAL1
Oscillator Select (D4). This bit determines which oscilla-
tor source is used to clock the internal POR and WDT
counter chain. If the bit is a "1", the internal RC oscillator is
bypassed and the POR and WDT clock source is driven
from the external pin, XTAL1. The default configuration of
this bit is 0, which selects the RC oscillator. If the XTAL1
pin is selected as the oscillator source for the WDT, during
STOP Mode, the oscillator will be stopped and the WDT
will not run. This is true even if the WDT is selected to run
during STOP Mode.
V
CC
Voltage Comparator. An on-board Voltage Compar-
ator checks that V
CC
is at the required level to ensure cor-
rect operation of the device. RESET is globally driven if
V
CC
is below the specified voltage (typically 2.6V).
ROM Protect. ROM Protect is mask or OTP bit-program-
mable. It is selected by the customer at the time the ROM
code is submitted.
ROM Mask Selectable Options
There are two ROM mask options that must be selected at
the time the ROM mask is ordered (ROM code submitted)
for the Z86C83/C84 and three Z86E83 OTP bit options.
Figure 39. Watch-Dog Timer Mode Register
(Write Only)
Table 15. WDT Time Select (Min. @ 5.0V)
D1 D0
Time-Out of
Internal RC OSC
Time-Out of
SCLK Clock
0 0 6.25 ms min 256 SCLK
0 1 12.5 ms min 512 SCLK
1 0 25 ms min 1024 SCLK
1 1 100 ms min 4096 SCLK
Note: The minimum time shown is for V
CC
@ 5.0V.
D7 D6 D5 D4 D3 D2 D1 D0
WDTMR (F) 0F
WDT TAP
00 256 SCLK
01 512 SCLK
10 1024 SCLK
11 4096 SCLK
WDT During HALT
0 OFF
1 ON
WDT During STOP
0 OFF
1 ON
XTAL1/INT RC Select for WDT
0 On-Board RC
1 XTAL
Reserved (Must be 0)
* Default setting after RESET
† XTAL=SCLK/TCLK shown
*
*
*
Table 16. Selectable Options
Option Selection
Permanent WDT Yes/No
ROM Protect Yes/No
EPROM/TEST Mode Disable* Yes/No
Note:
*For Z86E83 only
EPROM/TEST Mode Disable - On the Z86E83, the user can per-
manently disable entry into EPROM Mode and TEST Mode
by programming this bit.
