Z86E8316PEC Datasheet Z86E8316SEG, Z86E8316PSG, Z86E8316PEG | P34-P36

Z86C83/C84/E83

CMOS Z8

MCU Zilog

8-34 P R E L I M I N A R Y DS97DZ80700

FUNCTIONAL DESCRIPTION (Continued)

Analog-to-Digital Converter

The Analog-to-Digital (ADC) is an 8-bit half flash converter

that uses two reference resistor ladders for its upper 4 bits

(MSBs) and lower 4 bits (LSBs) conversion. Two reference

voltage pins, AV

and A

GND

, are provided for external

reference voltage supplies. During the sampling period

from one of the eight channel inputs, the converter is also

being auto-zeroed before starting the conversion. The

conversion time is dependent on the internal clock fre-

quency. The minimum conversion time is 35 x SCLK (see

Figure 22).

The ADC is controlled by the Z8 and its three registers (two

Control and one Result) are mapped into the Extended

the ADC Control Register 0 after the ADC Control Register

1 is configured.

The start command is implemented in such a way as to be-

gin a conversion at any time, if a conversion is in progress

and a new start command is received, then the conversion

in progress will be aborted and a new conversion will be

initiated. This allows the programmed values to be

changed without affecting a conversion-in-progress. The

new values will take effect only after a new start command

is received.

The ADC can be disabled (for low power) or enabled by a

Control Register bit.

Though the ADC will function for a smaller input voltage

and voltage reference, the noise and offsets remain con-

stant over the specified electrical range. The errors of the

converter will increase and the conversion time may also

take slightly longer due to smaller input signals.

ADC Calibration Offset

Specially matched resistors are program-enabled to allow

35 percent or 50 percent offset from A

GND

. They may se-

lectively enable these resistors to offset the A

GND

by 50

percent (2.5V to 5V) or 35 percent (1.75V to 5V) thereby

allowing the 8-bit ADC across a narrower voltage range.

This will allow significant resolution improvement within

the reduced voltage range.

Note: The AV

must be the same value as V

and

GND

must be the same value as GND.

Figure 22. ADC Architecture

Start

Converter

A/D

Control

Reg.

A/D

Result

Reg.

A/D

Converter

GND

A/D

Control

Reg.

Selected Channel

EXT

Sample

and Hold

ADC Register 9

D4, D5

Calibration Offset

ADC0

ADR1

ADC1

Vref + VCC

Vref- GND

Z86C83/C84/E83

Zilog CMOS Z8

MCU

DS97DZ80700 P R E L I M I N A R Y 8-35

Channel Select (bits 2, 1, 0)

* Default after reset

ADE (bit 7). A zero powers down and disables power and

any A/D conversions or accessing any ADC registers ex-

cept writing to ADE bit. A one Enables all ADC accesses.

ADC result register is shown in Figure 25.

Figure 23. ADC Control Register 0 (Read/Write)

SCAN

0 No action*

1 Convert channel then stop

CSEL2 CSEL1 CSEL0 Channel

0 0 0 0 (P20)*

0 0 1 1 (P21)

0 1 0 2 (P22)

0 1 1 3 (P23)

1 0 0 4 (P24)

1 0 1 5 (P25)

1 1 0 6 (P26)

1 1 1 7 (P27)

Note: ADCO D4 must equal 1 to allow Port bit as ADC input.

Figure 24. ADC Control Register 1 (Read/Write)

D7 D6 D5 D4 D3 D2 D1 D0

CSEL0

CSEL1

CSEL2

ADC0 (A) Bank C, Register 8

SCAN

0 = No action*.

1 = Convert, then stop.

/Input/Output Control

0 = No action*

1 = Enable selected channel

) as analog input

on associated Port 20-27

Must be D7 = 0

D6 = 0

D5 = 1

* Default after reset

D7 D6 D5 D4 D3 D2 D1 D0

ADC1 Bank C, Register 9

ADE

0 Disable*

1 Enable

Must be 0.

D5 D4

0 0 50 % AGND Offset

1 0 35% AGND Offset

0 1 Reserved

1 1 No Offset

Reserved (Must be 1)

* Default after reset

Figure 25. Result Register (Read-Only)

Figure 26. Bank C

Data

D7 D6 D5 D4 D3 D2 D1 D0

ADR Bank C, Register A

Reg F

Reg E

Reg D

Reg C

Reg B

Reg A

Reg 9

Reg 8 AD Control 0

Reg 7

Reg 6

Reg 5

Reg 4

Reg 3

Reg 2

Reg 1

Reg 0

AD Control 1

AD Result 1

These registers

can be accessed.

Z86C83/C84/E83

CMOS Z8

MCU Zilog

8-36 P R E L I M I N A R Y DS97DZ80700

FUNCTIONAL DESCRIPTION (Continued)

Figure 27 shows the input circuit of the ADC. When con-

version starts the analog input voltage is connected to the

MSB and LSB flash converter inputs as shown in the Input

Impedance CKT diagram. Effectively, shunting 31 parallel

internal resistance of the analog switches and simulta-

neously charging 31 parallel 0.5 pF capacitors, which is

equivalent to seeing a 400 Ohms input impedance in par-

allel with a 16 pF capacitor. Other input stray capacitance

adds about 10 pF to the input load. For input source resis-

tances up to 2 Kohms can be used under normal operating

condition without any degradation of the input settling time.

For larger input source resistance, increasing conversion

cycle time or adding a capacitor to the input may be re-

quired to compensate the input settling time problem.

Typical Z8 A/D Conversion Sequence

3. Set the register pointer to Extended Bank (C), that is,

SRP #%0C instruction.

4. Next, set ADE flag by loading ADC1 Control Register

Bank (C) Register 9, bit 7. Also, load bits 0-4 of this

same register to select a AV

or A

GND

offset value. A

precision voltage divider connected to the A/D

resistive ladder can offset conversion dynamic range

to specified limits within the AV

and A

GND

limits. By

loading Bank (C) Register 9, bits 0-4, with the

appropriate value it is possible to select from these

groups:

a. No Offset. The Converter Dynamic range is from

0V to 5.0V for AV

= 5.0V.

b. 35 Percent A

GND

Offset. The Converter Dynamic

range is 1.75V - 5.0V for AV

= 5.0V.

c. 50 Percent A

GND

Offset. The Converter Dynamic

range is 2.5V - 5.0V for AV

= 5.0V.

5. Select one of the eight A/D inputs for conversion by

loading Bank (C) Register 8 with the desired attributes:

Bits 0 - 2 select an A/D input, bits 3 and 4 select A/D

conversion (or digital port I/O).

6. Set Bank (C) Register 8, bit 3 to enable A/D

conversion. (This flag can be set concurrently with

step 3.) This flag is automatically reset when the A/D

conversion is completed, so a bit test can be

performed to determine A/D readiness if necessary.

7. Read the A/D result in Bank (C) Register A. Please

note that the A/D result is not valid (indeterminate)

unless ADE flag (Register 9, bit 7) was previously set,

otherwise A/D converter output is tri-stated.

Figure 27. Input Impedance of ADC

CMOS Switch

on Resistance

2 - 5 k Ω

C Parasitic

R Source

C .5 pF

V Ref

C .5 pF

31 CMOS Digital

Comparators

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P52

Z86E8316PEC

Mfr. #:

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8-bit Microcontrollers - MCU 4K OTP 16MHz W/ADC

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Z86E8316PEC

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