OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

CV125PAG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
COMMERCIAL TEMPERATURE RANGE
10
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
BYTE 13
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 48MHzStr0 RW 0
1 48MHStr1 USB48MHz0 strength selection RW 0
2 REFStr0 RW 0
3 REFStr1 REF strength selection RW 0
4 PCIStrC0 RW 0
5 PCIStrC1 PCI strength selection RW 0
6 PCIFStr0 RW 0
7 PCIFStr1 PCIF strength selection RW 0
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VIH Input HIGH Voltage 3.3V ± 5% 2 — VDD + 0.3 V
VIL Input LOW Voltage 3.3V ± 5% VSS - 0.3 — 0.8 V
VIH_FS LOW Voltage, HIGH Threshold For FSA.B.C test_mode 0.7 — VDD + 0.3 V
VIL_FS LOW Voltage, LOW Threshold For FSA.B.C test_mode VSS - 0.3 — 0.35 V
IIH Input HIGH Current VIN = VDD –5 — 5 µ A
IIL1 Input LOW Current VIN = 0V, inputs with no pull-up resistors –5 — — µA
IIL2 Input LOW Current VIN = 0V, inputs with pull-up resistors –200 — — µA
IDD3.3OP Operating Supply Current Full active, CL = full load — — 400 mA
I
DD3.3PD Powerdown Current All differential pairs driven — — 70 mA
All differential pairs tri-stated — — 12
FI Input Frequency
(1)
VDD = 3.3V — 14.31818 — MHz
LPIN Pin Inductance
(2)
—— 7 nH
CIN Logic inputs — — 5
C
OUT Input Capacitance
(2)
Output pin capacitance — — 6 pF
C
INX XTAL_IN — — 5
COUTX XTAL_OUT — — 12
TSTAB Clock Stabilization
(2,3)
From VDD power-up or de-assertion of PD to first clock — — 1.8 ms
Modulation Frequency
(2)
Triangular modulation 30 — 33 KHz
TDRIVE_SRC
(2)
SRC output enable after PCI_STOP# de-assertion — — 15 ns
TDRIVE_PD
(2)
CPU output enable after PD de-assertion — — 300 us
TFALL_PD
(2)
Fall time of PD — — 5 ns
TRISE_PD
(3)
Rise time of PD — — 5 ns
TDRIVE_CPU_STOP#
(2)
CPU output enable after CPU_STOP# de-assertion — — 10 us
TFALL_CPU_STOP#
(2)
Fall time of CPU_STOP# — — 5 ns
TRISE_CPU_STOP#
(3)
Rise time of CPU_STOP# — — 5 ns
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%
NOTES:
1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
2. This parameter is guaranteed by design, but not 100% production tested.
3. See TIMING DIAGRAMS for timing requirements.
COMMERCIAL TEMPERATURE RANGE
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
11
Symbol Parameter Test Conditions Min. Typ. Max. Unit
ZO Current Source Output Impedance
(2)
VO = VX 3000 — — Ω
VOH3 Output HIGH Voltage IOH = -1mA 2.4 — — V
VOL3 Output LOW Voltage IOL = 1mA — — 0.4 V
V
HIGH Voltage HIGH
(2)
Statistical measurement on single-ended signal using 660 — 1150 mV
VLOW Voltage LOW
(2)
oscilloscope math function –300 — 150
V
OVS Max Voltage
(2)
Measurement on single-ended signal using absolute value — — 1150 mV
VUDS Min Voltage
(2)
–300 — —
VCROSS(ABS) Crossing Voltage (abs)
(2)
250 — 550 mV
d - VCROSS Crossing Voltage (var)
(2)
Variation of crossing over all edges — — 140 mV
ppm Long Accuracy
(2,3)
See TPERIOD Min. - Max. values –300 — 300 ppm
400MHz nominal / -0.5% spread 2.4993 — 2.5133
333.33MHz nominal / -0.5% spread 2.9991 — 3.016
266.66MHz nominal / -0.5% spread 3.7489 — 3.77
TPERIOD Average Period
(3)
200MHz nominal / -0.5% spread 4.9985 — 5.0266 ns
166.66MHz nominal / -0.5% spread 5.9982 — 6.032
133.33MHz nominal / -0.5% spread 7.4978 — 7.54
100MHz nominal / -0.5% spread 9.997 — 10.0533
96MHz nominal 10.4135 — 10.4198
400MHz nominal / -0.5% spread 2.4143 — —
333.33MHz nominal / -0.5% spread 2.9141 — —
266.66MHz nominal / -0.5% spread 3.6639 — —
200MHz nominal / -0.5% spread 4.9135 — —
T
ABSMIN Absolute Min Period
(2,3)
166.66MHz nominal / -0.5% spread 5.9132 — — ns
133.33MHz nominal / -0.5% spread 7.4128 — —
100MHz nominal / -0.5% spread 9.912 — —
96MHz nominal 10.1635 — —
tR Rise Time
(2)
VOL = 0.175V, VOH = 0.525V 175 — 700 ps
tF Fall Time
(2)
VOL = 0.175V, VOH = 0.525V 175 — 700 ps
d-tR Rise Time Variation
(2)
— — 125 ps
d-tF Fall Time Variation
(2)
— — 125 ps
dT3 Duty Cycle
(2)
Measurement from differential waveform 45 — 55 %
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE
DIFFERENTIAL PAIR
(1)
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
NOTES:
1. SRC clock outputs run only at 100MHz.
2. This parameter is guaranteed by design, but not 100% production tested.
3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
COMMERCIAL TEMPERATURE RANGE
12
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
Symbol Parameter Test Conditions Min. Typ. Max. Unit
ppm Static Error
(1,2)
See Tperiod Min. - Max. values — — 0 ppm
T
PERIOD Clock Period
(2)
33.33MHz output nominal 29.991 — 30.009 ns
33.33MHz output spread 29.991 — 30.1598
VOH Output HIGH Voltage IOH = -1mA 2.4 — — V
VOL Output LOW Voltage IOL = 1mA — — 0.55 V
I
OH Output HIGH Current VOH at Min. = 1V -33 — — mA
VOH at Max. = 3.135V — — -33
I
OL Output LOW Current VOL at Min. = 1.95V 30 — — mA
VOL at Max. = 0.4V — — 38
Edge Rate
(1)
Rising edge rate 1 — 4 V/ns
Edge Rate
(1)
Falling edge rate 1 — 4 V/ns
tR1 Rise Time
(1)
VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns
tF1 Fall Time
(1)
VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns
dT1 Duty Cycle
(1)
VT = 1.5V 45 — 55 %
tSK1 Skew
(1)
VT = 1.5V — — 500 ps
t
JCYC-CYC Jitter, Cycle to Cycle
(1)
VT = 1.5V — — 500 ps
ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE
DIFFERENTIAL PAIR, CONTINUED
(1)
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
Skew, CPU[1:0]
(2)
— — 100
t
SK3 Skew, CPU2
(2)
VT = 50% — — 250 ps
Skew, SRC
(2)
— — 250
Jitter, Cycle to Cycle, CPU[1:0]
(2)
—— 85
tJCYC-CYC Jitter, Cycle to Cycle, CPU2
(2)
Measurement from differential waveform — — 100 ps
Jitter, Cycle to Cycle, SRC
(2)
— — 125
Jitter, Cycle to Cycle, DOT96
(2)
— — 250
NOTES:
1. SRC clock outputs run only at 100MHz.
2. This parameter is guaranteed by design, but not 100% production tested.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

CV125PAG

Mfr. #:
Buy CV125PAG
Manufacturer:
IDT
Description:
Phase Locked Loops - PLL FlexPC Clock Programmer P4
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet