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CV125PAG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
COMMERCIAL TEMPERATURE RANGE
4
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
PIN DESCRIPTION (CONT.)
Pin Number Name Type Description
43 CPU0# OUT Host 0.7 current mode differential clock output
44 CPU0 OUT Host 0.7 current mode differential clock output
45 V SS_CPU GND GND
46 SCL IN SM bus clock
47 SDA I/O SM bus data
48 VDD_REF PWR 3.3V
49 XTAL_OUT OUT XTAL output
50 XTAL_IN I N XTAL input
51 VSS_REF GND GND
52 REF OUT 14.318 MHz reference clock output
53 FSC/TEST_SEL IN CPU frequency selection. Selects test mode if pulled above 2V when VTT_PWRGD# is asserted LOW.
54 CPU_STOP# IN Stop all stoppable CPU CLK
55 PCI_STOP# IN Stop all stoppable PCI, SRC CLK
56 PCI0 OUT PCI clock
INDEX BLOCK WRITE PROTOCOL
Bit # of bits From Description
1 1 Master Start
2-9 8 Master D2h
10 1 Slave Ack (Acknowledge)
11-18 8 Master Register offset byte (starting byte)
19 1 Slave Ack (Acknowledge)
20-27 8 Master Byte count, N (0 is not valid)
28 1 Slave Ack (Acknowledge)
29-36 8 Master first data byte (Offset data byte)
37 1 Slave Ack (Acknowledge)
38-45 8 Master 2nd data byte
46 1 Slave Ack (Acknowledge)
:
Master Nth data byte
Slave Acknowledge
Master Stop
INDEX BLOCK READ PROTOCOL
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit30-37).
Bit # of bits From Description
1 1 Master Start
2-9 8 Master D2h
10 1 Slave Ack (Acknowledge)
11-18 8 Master Register offset byte (starting byte)
19 1 Slave Ack (Acknowledge)
20 1 Master Repeated Start
21-28 8 Master D3h
29 1 Slave Ack (Acknowledge)
30-37 8 Slave Byte count, N (block read back of N
bytes), power on is 8
38 1 Master Ack (Acknowledge)
39-46 8 Slave first data byte (Offset data byte)
47 1 Master Ack (Acknowledge)
48-55 8 Slave 2nd data byte
Ack (Acknowledge)
:
Master Ack (Acknowledge)
Slave Nth data byte
Not acknowledge
Master Stop
INDEX BYTE WRITE
Setting bit[11:18] = starting address, bit[20:27] = 01h.
INDEX BYTE READ
Setting bit[11:18] = starting address. After reading back the first data byte,
master issues Stop bit.
COMMERCIAL TEMPERATURE RANGE
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
5
SSC MAGNITUDE CONTROL FOR CPU,
SRC, AND SMC
SMC[2:0]
000 -0.25
001 -0.5
010 -0.75
011 -1
100 ±0.125
101 ±0.25
110 ±0.375
111 ±0.5
SEL 100/96# CONFIGURATION
SEL 100/96# LVDS Frequency Unit
0 96 MHz
1 100 MHz
SPREAD SPECTRUM CONTROL
SELECTION (SSC) FOR LVDS
S[3:0] Spread
0000 -0.8%
0001 -1%
0010 -1.25%
0011 -1.5%
0100 -1.75%
0101 -2%
0110 -0.3%
0111 -0.5%
1000 ±0.3%
1001 ±0.4%
1010 ±0.5%
1011 ±0.6%
1100 ±0.8%
1101 ±1%
1110 ±1.25%
1111 ±1.5%
S.E. CLOCK STRENGTH SELECTION
(PCI, REF, USB48)
Str[1:0] Level
00 1
01 0.8
10 0.6
11 1.2
RESOLUTION
CPU (MHz) Resolution N =
100 0.666667 150
133 0.666667 200
166 1.333333 125
200 1.333333 150
266 1.333333 200
333 2.666667 125
400 2.666667 150
COMMERCIAL TEMPERATURE RANGE
6
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
BYTE 0
Bit Output(s) Affected Description/Function 0 1 Type Power On
0 Reserved
1 SRC1, SRC1# Output Enable Tristate Enable RW 1
2 SRC2, SRC2# Output Enable Tristate Enable RW 1
3 SRC3, SRC3# Output Enable Tristate Enable RW 1
4 SRC4, SRC4# Output Enable Tristate Enable RW 1
5 SRC5, SRC5# Output Enable Tristate Enable RW 1
6 SRC6, SRC6# Output Enable Tristate Enable RW 1
7 CPU2, CPU2#/ Output Enable Tristate Enable RW 1
SRC7, SRC7#
BYTE 1
Bit Output(s) Affected Description/Function 0 1 Type Power On
0 CPU[2:0], SRC[7:1], Spread Spectrum mode enable Spread off Spread on RW 0
PCI[5:0], PCIF[1:0]
1 CPU0, CPU0# Output Enable Tristate Enable RW 1
2 CPU1, CPU1# Output Enable Tristate Enable RW 1
3 Reserved RW 0
4 REF Output Enable Tristate Enable RW 1
5 USB48 Output Enable Tristate Enable RW 1
6 DOT96 Output Enable Tristate Enable RW 1
7 PCIF0 Output Enable Tristate Enable RW 1
BYTE 2
Bit Output(s) Affected Description/Function 0 1 Type Power On
0 PCIF1 Output Enable Tristate Enable RW 1
1 Reserved RW 1
2 PCI0 Output Enable Tristate Enable RW 1
3 PCI1 Output Enable Tristate Enable RW 1
4 PCI2 Output Enable Tristate Enable RW 1
5 PCI3 Output Enable Tristate Enable RW 1
6 Reserved RW 1
7 Reserved RW 1
CONTROL REGISTERS
N PROGRAMMING PROCEDURE
• Use Index byte write.
• For N programming, the user only needs to access Byte 11, Byte 12, and Byte 9.
1. Write Byte 11 for CPU PLL N, CPU f = N* Resolution (see resolution table).
2. Write Byte 12 for SRC PLL N, SRC f = N*0.666667, PCI = SRC f /3.
3. Enable N Programming bit, Byte 9 bit 1. Once this bit is enabled, any N value will be changed on the fly.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

CV125PAG

Mfr. #:
Buy CV125PAG
Manufacturer:
IDT
Description:
Phase Locked Loops - PLL FlexPC Clock Programmer P4
Lifecycle:
New from this manufacturer.
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