COMMERCIAL TEMPERATURE RANGE
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
19
Symbol Parameter Min. Typ. Max. Unit
tR1 Clock Rise Time
(1,2,3)
175 700 ps
tF1 Clock Fall Time
(1,2,3)
175 700 ps
tR Clock Rise Time Variation
(2,3,4)
125 ps
tF Clock Fall Time Variation
(2,3,4)
125 ps
Rise/Fall Matching
(2,3,5)
—— 20%
VHIGH Voltage HIGH
(2,3,6)
660 700 850 mV
VLOW Voltage LOW
(2,3,7)
-150 0 mV
VCROSS(ABS) Crossing Voltage (abs)
(2,3,8,9,10)
250 550 mV
VCROSS(REL) Crossing Voltage (rel)
(2,3,10,11)
Calc. Calc.
TOTAL VCROSS Total Variation of VCROSS Over All Edges
(2,3,12)
140 mV
tJCYC-CYC Cycle-to-Cycle Jitter
(2,13)
350 ps
dT3 Duty Cycle
(2,13)
45 55 %
VOVS Maximum Voltage Allowed at Output (overshoot)
(2,3,14)
——VHIGH + 0.3V V
VUDS Minimum Voltage Allowed at Output (undershoot)
(2,3,15)
-0.3 V
V
RB Ringback Margin
(2,3)
n/a 0.2 V
LVDS AC TIMING REQUIREMENTS
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C
NOTES:
1. Measured from VOL = 1.75V to VOH =0.525V. Only valid for Rising LVDS and Falling LVDS#. Signal must be monotonic through the VOL to VOH region for tRISE and tFALL.
2. Test configuration is Rs = 32.2, Rp = 49.9, 2pF.
3. Measurement taken from single-ended waveform.
4. Measured with oscilloscope, averaging off, using Min. Max. statistics. Variation is the delta between Min. and Max.
5. Measured with oscilloscope, averaging off, the difference between the tRISE (average) of LVDS versus the tFALL (average) of LVDS#.
6. VHIGH is defined as the statistical average HIGH value as obtained by using the oscilloscope VHIGH math function.
7. VLOW is defined as the statistical average LOW value as obtained by using the oscilloscope VLOW math function.
8. Measured at crossing point where the instantaneous voltage value of the rising edge of LVDS equals the falling edge of LVDS#.
9. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
10. The crossing point must meet the absolute and relative crossing point specifications simultaniously.
11. VCROSS (rel) Min. and Max. are derived using the following: VCROSS (rel) Min. = 0.25V + 0.5 (VHAVG - 0.7V), VCROSS (rel) Max. = 0.55V + 0.5 (0.7V - VHAVG).
12. VCROSS is defined as the total variation of all crossing voltages of Rising LVDS and Falling LVDS#. This is the maximum allowed variance in VCROSS for any particular system.
13. Measurement is taken from differential waveform.
14. Overshoot is defined as the absolute value of the maximum voltage.
15. Undershoot is defined as the absolute value of the minimum voltage.
COMMERCIAL TEMPERATURE RANGE
20
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
96MHz 100MHz
Spread Min. Max. Min. Max. Unit
0% (no spread) 10.406 10.427 9.99 10.01 ns
0.8% down-spread 10.406 10.511 9.99 10.09 ns
1% down-spread 10.406 10.531 9.99 10.11 ns
1.25% down-spread 10.406 10.557 9.99 10.135 ns
1.5% down-spread 10.406 10.583 9.99 10.16 ns
1.75% down-spread 10.406 10.61 9.99 10.185 ns
2% down-spread 10.406 10.636 9.99 10.21 ns
2.5% down-spread 10.406 10.688 9.99 10.26 ns
3% down-spread 10.406 10.74 9.99 10.31 ns
±0.3% down-spread 10.375 10.458 9.96 10.04 ns
±0.4% down-spread 10.365 10.469 9.95 10.05 ns
±0.5% down-spread 10.354 10.479 9.94 10.06 ns
±0.6% down-spread 10.344 10.49 9.93 10.07 ns
±0.8% down-spread 10.323 10.511 9.91 10.09 ns
±1% down-spread 10.302 10.531 9.89 10.11 ns
±1.25% down-spread 10.276 10.557 9.865 10.135 ns
±1.5% down-spread 10.25 10.583 9.84 10.16 ns
LVDS AVERAGE PERIOD, TPERIOD
(1,2,3,4)
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C
NOTES:
1. Test configuration is Rs = 32.2, Rp = 49.9, 2pF.
2. The average period over any 1µS period of tiime must be greater than the minimum and less than the maximum specified period.
3. Measurement is taken from differential waveform.
4. Calculated using a ±0.1% accuracy in spread modulation. Assumes 300ppm long term accuracy on CLKIN.
Single-Ended Measurement Point for tRISE and tFALL
VOH = 0.525V
VC
ROSS
VOL = 0.175V
t
RISE (LVDS)
t
FALL (LVDS#)
LVDS#
LVDS
COMMERCIAL TEMPERATURE RANGE
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
21
Symbol Parameter Min. Typ. Max. Unit
t
PZL Output Enable Delay (All Outputs)
(1)
0—10µs
tPZH
tPLZ Output Disable Delay (All Outputs)
(1)
0—10µs
tPHZ
tSTABLE All Clock Stabilization from Power-Up
(2)
——3ms
t
SPREAD Setting Period for Spread Selection Change
(2,3)
——3ms
MISCELLANEOUS AC TIMING REQUIREMENTS
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C
NOTES:
1. These specifications apply to the LVDS and SMBus pins. These pins must be tri-stated when PWRDWN is asserted. LVDS is driven differential when PWRDWN is de-asserted unless
it is disabled.
2. The time specified is from when V
DD achieves its nominal operating level (typical condition VDD = 3.3V) and PWRDWN is de-asserted until the frequency output is stable and operating
within specification.
3. The time specified is measured from the spread selection change or output frequency change until the LVDS clock is operating at the new spread modulation and frequency.
If there is another change in spread selection or output frequency during the t
SPREAD settling period, then the settling period start resets to the most recent change in spread selection
and output frequency.

CV125PAG

Mfr. #:
Manufacturer:
IDT
Description:
Phase Locked Loops - PLL FlexPC Clock Programmer P4
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet