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CV125PAG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
COMMERCIAL TEMPERATURE RANGE
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
7
BYTE 3
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 Reserved RW 0
1 SRC1 RW 0
2 SRC2 RW 0
3 SRC3 Allow controlled by Free running, not Stopped with RW 0
4 SRC4 PCI_STOP# assertion affected by PCI_STOP# PCI_STOP# RW 0
5 SRC5 RW 0
6 SRC6 RW 0
7 SRC7 RW 0
BYTE 5
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 CPU0, CPU0# CPU0 PD drive mode Driven in power down Tristate in power down RW 0
1 CPU1, CPU1# CPU1 PD drive mode Driven in power down Tristate in power down RW 0
2 CPU2, CPU2# CPU2 PD drive mode Driven in power down Tristate in power down RW 0
3 SRC[7:1], SRC[7:1]# SRC PD drive mode Driven in power down Tristate in power down RW 0
4 CPU0, CPU0# CPU0 CPU_STOP drive mode Driven in CPU_STOP# Tristate when stopped RW 0
5 CPU1, CPU1# CPU1 CPU_STOP drive mode Driven in CPU_STOP# Tristate when stopped RW 0
6 CPU2, CPU2# CPU2 CPU_STOP drive mode Driven in CPU_STOP# Tristate when stopped RW 0
7 SRC[7:1], SRC[7:1]# SRC PCI_STOP drive mode Driven in PCI_STOP Tristate when stopped RW 0
BYTE 4
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 CPU0, CPU0# Allow control of CPU0 Not stopped Stopped with RW 1
with assertion of CPU_STOP# by CPU_STOP# CPU_STOP#
1 CPU1, CPU1# Allow control of CPU1 Not stopped Stopped with RW 1
with assertion of CPU_STOP# by CPU_STOP# CPU_STOP#
2 CPU2, CPU2# Allow control of CPU2 Not stopped Stopped with RW 1
with assertion of CPU_STOP# by CPU_STOP# CPU_STOP#
3 PCIF0 Allow controlled by Not stopped Stopped with RW 0
4 PCIF1 PCI_STOP# assertion by PCI_STOP# PCI_STOP# RW 0
5 Reserved RW 0
6 DOT96 DOT96 power down drive mode Driven in power down Tristate RW 0
7 Reserved RW 0
COMMERCIAL TEMPERATURE RANGE
8
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
BYTE 6
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 CPU[2:0] FSA latched value on power up R
1 CPU[2:0] FSB latched value on power up R
2 CPU[2:0] FSC latched value on power up R
3 PCI, SRC Software PCI_STOP control for Stop all PCI, PCIF, and Software STOP RW 1
PCI and SRC CLK SRC which can be stopped Disabled
by PCI_STOP#
4 REF REF drive strength 1x drive 2x drive RW 1
5 Reserved RW 0
6 Test clock mode entry control Normal operation Test mode, controlled RW 0
by Byte 6, Bit 7
7 CPU, SRC, PCI Only valid when Byte 6, Bit 6 Hi-Z REF/N RW 0
PCIF, REF, is HIGH
USB48, DOT96
BYTE 7
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 Vendor ID R 1
1 Vendor ID R 0
2 Vendor ID R 1
3 Vendor ID R 0
4 Revision ID R 0
5 Revision ID R 0
6 Revision ID R 0
7 Revision ID R 0
BYTE 8, LVDS CONTROL BYTE
Bit Output(s) Affected Description/Function 0 1 Type Power On
0 LVDS HW/ SMBus control HW
(1)
SW RW 0
1 LVDS SSC EN Spread spectrum enable Off On RW 1
2 LVDS Enable Output Enable Disable Enable RW 1
3 SEL 100/96# Select LVDS frequency 96MHz 100MHZ RW SEL 100/96#
4 S3 see SSC table RW 0
5 S2 see SSC table RW 0
6 S1 see SSC table RW 0
7 S0 see SSC table RW 0
NOTE:
1. If bit 0 is set to 0, LVDS output frequency is selected by HW SEL 100/96#. If bit 0 is set to 1, LVDS output frequency is selected by bit 3.
COMMERCIAL TEMPERATURE RANGE
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
9
BYTE 9
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 One cycle read disable enable RW 0
1 N Programming enable Disable enable RW 0
2 LVDS PLL power down normal Power down RW 0
3 RW 0
4 USB PLL power down normal Power down RW 0
5 SRC PLL power down normal Power down RW 0
6 CPU PLL power down normal Power down RW 0
7 SRC, PLL2, SSC enable Only valid when Byte1 bit0 is 1 disable enable RW 1
BYTE 11
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 CPU_N0, LSB CPU CLK = N* Resolution RW 0
1 CPU_N1 see Resolution table RW 1
2 CPU_N2 RW 1
3 CPU_N3 RW 0
4 CPU_N4 RW 1
5 CPU_N5 RW 0
6 CPU_N6 RW 0
7 CPU_N7, MSB RW 1
BYTE 10
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 SRC SMC0 SRC/PCI SSC control RW 1
1 SRC SMC1 see SMC table RW 0
2 SRC SMC2 RW 0
3 Reserved RW 0
4 CPU SMC0 CPU PLL SSC control RW 1
5 CPU SMC1 see SMC table RW 0
6 CPU SMC2 RW 0
7 Reserved RW 0
BYTE 12
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 SRC_N0, LSB RW 0
1 SRC_N1 RW 1
2 SRC_N2 SRC f = N*SRC Resolution RW 1
3 SRC_N3 Resolution = 0.666667 RW 0
4 SRC_N4 100MHz N= 150 RW 1
5 SRC_N5 RW 0
6 SRC_N6 RW 0
7 SRC_N7, MSB RW 1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

CV125PAG

Mfr. #:
Buy CV125PAG
Manufacturer:
IDT
Description:
Phase Locked Loops - PLL FlexPC Clock Programmer P4
Lifecycle:
New from this manufacturer.
Delivery:
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