FEDS5412222B-02
LAPIS Semiconductor
MSM5412222B
10/16
Notes: 1. Input signal reference levels for the parameter measurement are V
IH
= 3.0 V and V
IL
= 0 V. The
transition time t
T
is defined to be a transition time that signal transfers between V
IH
= 3.0 V and
V
IL
= 0 V.
2. AC measurements assume t
T
= 3 ns.
3. Read address must have more than a 150 address delay than write address in every cycle
when asynchronous read/write is performed.
4. Read must have more than a 150 address delay than write in order to read the data written in
a current series of write cycles which has been started at last write reset cycle: this is called
“new data read”.
When read has less than a 20 address delay than write, the read data are the data written in a
previous series of write cycles which had been written before at last write reset cycle: this is
called “old data read”.
5. When the read address delay is between more than 21 and less than 149, read data will be
undetermined. However, normal write is achieved in this address condition.
6. Outputs are measured with a load equivalent to 1 TTL load and 30 pF.
Output reference levels are V
OH
= 2.0 V and V
OL
= 0.8 V.
