FEDS5412222B-02
LAPIS Semiconductor
MSM5412222B
7/16
Power-up and Initialization
On power-up, the device is designed to begin proper operation after at least 100 s after V
CC
has stabilized to a
value within the range of recommended operating conditions. After this 100 s stabilization interval, the following
initialization sequence must be performed.
Because the read and write address counters are not valid after power-up, a minimum of 80 dummy write
operations (SWCK cycles) and read operations (SRCK cycles) must be performed, followed by an RSTW
operation and an RSTR operation, to properly initialize the write and the read address pointer. Dummy write
cycles/RSTW and dummy read cycles/RSTR may occur simultaneously.
If these dummy read and write operations start while V
CC
and/or the substrate voltage has not stabilized, it is
necessary to perform an RSTR operation plus a minimum of 80 SRCK cycles plus another RSTR operation, and an
RSTW operation plus a minimum of 80 SRCK cycles plus another RSTW operation to properly initialize read and
write address pointers.
Old/New Data Access
There must be a minimum delay of 150 SWCK cycles between writing into memory and reading out from memory.
If reading from the first field starts with an RSTR operation, before the start of writing the second field (before the
next RSTW operation), then the data just written will be read out.
The start of reading out the first field of data may be delayed past the beginning of writing in the second field of
data for as many as 20 SWCK cycles. If the RSTR operation for the first field read-out occurs less than 20 SWCK
cycles after the RSTW operation for the second field write-in, then the internal buffering of the device assures that
the first field will still be read out. The first field of data that is read out while the second field of data is written is
called “old data”.
In order to read out “new data”, i.e., the second field written in, the delay between an RSTW operation and an
RSTR operation must be at least 150 SRCK cycles. If the delay between RSTW and RSTR operations is more than
21 but less than 150 cycles, then the data read out will be undetermined. It may be “old data” or “new” data, or a
combination of old and new data. Such a timing should be avoided.
Cascade Operation
The MSM5412222B is designed to allow easy cascading of multiple memory devices. This provides higher
storage depth, or a longer delay than can be achieved with only one memory device.
