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XRD9826ACD-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
XRD9826
10
Rev. 1.10
The DC reference voltage applied to VDCEXT does not
have to be accurate. The internal offset DAC voltage
is still used in this mode for fine adjustment. VDCEXT
Figure 4. Application with Offset Greater Than (-100mv to 500mv)
RL
VRT
VRB
VDD
RED
XRD9826
DC
REFERENCE
C
I
S
M
U
X
N/C
N/C
VDCEXT
cannot be used as an input from the CIS. Any signal
applied to VDCEXT will be subtracted from the output
signal of the multiplexer.
XRD9826
11
Rev. 1.10
Figure 5. Typical Application Circuitry CIS DC Coupled Non-Inverted Mode
AGND
DVDD (3V - 5V)
VCC (5V - 15V)
AVDD
DGND
AVDD
ASIC
DIGITAL
C
I
S
N/C
N/C
4K
0.1uF
0.01uF
0.1uF
0.01uF
0.1uF
0.1uF
1K
XRD9826
DVDD
1
DB0
2
DB1
3
DB2
4
DB3
5
DB4
6
DB5/SCLK
7
DB6/SDATA
8
DB7/LD
9
DGND
10
ADCCLK
11
CLAMP
12
SYNCH
13
AGND
14
VREF+
15
VDCEXT
16
BLU
17
GRN
18
RED
19
AVDD
20
XRD9826
12
Rev. 1.10
Mode 2. AC Coupled
If the CIS signal has a black reference for the video
signal, an external capacitor C
EXT
is used. When
CLAMP (clamp) pin is set high an internal switch allows
one side of the external capacitor to be set to ground.
It then is level shifted to correspond to the bottom ladder
reference voltage of the ADC (Figure 7).
ADCCLK Events
↓ ADC Sample & PGA Start Tracking next Pixel
MSB Data Out
↑ LSB Data Out
HI ADC Track PGA Output
LO ADC Hold/Convert
Table 1.
CIS Mode Timing -- DC Coupled
(CLAMP disabled)
ADCCLK
tckhw tcklw
tckpd
tap
tap
Pixel N-1 Pixel N
tdv
Pixel N+1
CIS
tdv
[5:0]
[11:6]
N-8
MSB
N-8
LSB
N-7
MSB
N-7
LSB
N-6
MSB
N-6
LSB
N-5
MSB
N-5
LSB
DB
Figure 6. Timing Diagram for Figure 5
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

XRD9826ACD-F

Mfr. #:
Buy XRD9826ACD-F
Manufacturer:
MaxLinear
Description:
Analog to Digital Converters - ADC
Lifecycle:
New from this manufacturer.
Delivery:
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