XRD9826
24
Rev. 1.10
ADCCLK Events
3rd ↓ Simultaneous RED/GRN/BLU Sample Every 3rd CLK.
Convert RED, S/H GRN, S/H BLU.
All ↓ MSB Data Out (8 upper bits)
↑ LSB Data Out (8 lower bits)
HI ADC Track PGA Output
LO ADC Hold/Convert
CLAMP Events
HI Internal Clamp Enabled
LO Internal RED/GRN/BLU Tracking Enabled
SYNCH Events
HI Reset Internal Mux to Red, Ouput Bus is Tri-stated
LO Increment Mux Color on Falling Edge of ADCCLK
Table 5.
Figure 18. Timing Diagram for Figure 17
Note: There is an 8 clock latency at the output.
(CLAMP Enabled)
BLU
GRN
RED
ADCCLK
CLAMP
DATA
PIXEL-BY-PIXEL 3 CHANNEL CCD -- AC Coupled
tdv
RED (N-6)
MSB
N+1 Pixel
CONVERT
RED (N)
CONVERT
GRN (N)
CONVERT
BLU (N)
TRACK
RED (N)
TRACK
GRN (N)
TRACK
RED (N+1)
TRACK
BLU (N)
CONVERT
RED (N+1)
tdv
tdv tdvtdv
RED (N-6)
LSB
GRN (N-6)
MSB
GRN (N-6)
LSB
BLU (N-6)
MSB
BLU (N-6)
LSB
CLAMP
tsa
SYNCH
tsypw
tclp=10ns
tap
tclp=10ns
N+1 Pixel
N+1 Pixel
N Pixel
N Pixel
N Pixel
Simultaneous
Sample
trars
