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XRD9826ACD-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
XRD9826
13
Rev. 1.10
This value corresponds to the black reference of the
image sensor. When the CLAMP pin is set back to low,
the ADC samples the video signal with respect to the
black reference. The typical value for the external
capacitor is 100pF. This value should be adjusted
according to the time constant (Tc) needed in a
particular application. The CLAMP pin has an internal
150 ohm impedance (R
INT
) which is in series with the
external capacitor (C
EXT
).
Figure 7. CIS AC Coupled Application
Therefore, Tc =1/R
INT
C
EXT
If the input to the external capacitor has a source
impedance (R
EXT
), then:
T
c
=1/(R
INT
+R
EXT
)C
EXT
RL
VRT
VRB
VDD
XRD9826
CLAMP
RINT
RED
M
U
X
C
I
S
REXT
CEXT
N/C
N/C
N/C
XRD9826
14
Rev. 1.10
DVDD (3V - 5V)
AVDD
VCC (5V - 15V)
DGND
AGND
DIGITAL
ASIC
C
I
S
N/C
N/C
N/C
100PF
0.1uF
0.1uF
0.01uF
0.1uF
0.01uF
XRD9826
DVDD
1
DB0
2
DB1
3
DB2
4
DB3
5
DB4
6
DB5/SCLK
7
DB6/SDATA
8
DB7/LD
9
DGND
10
ADCCLK
11
CLAMP
12
SYNCH
13
AGND
14
VREF+
15
VDCEXT
16
BLU
17
GRN
18
RED
19
AVDD
20
Figure 8. Typical Application Circuitry CIS AC Coupled Non-Inverted
XRD9826
15
Rev. 1.10
CIS Mode Timing -- AC Coupled
(CLAMP enabled)
ADCCLK
tckhw tcklw
tckpd
tap
tap
Pixel N-1 Pixel N
tdv
Pixel N+1
CIS
tdv
[5:0]
[11:6]
N-8
N-8
LSB
N-7
N-7
LSB
N-6
N-6
LSB
N-5 N-5
LSB
CLAMP
tclpw
MSB MSB MSB MSB
DB
Figure 9. Timing Diagram for Figure 8.
ADCCLK Events
↓ ADC Sample & PGA Start Track of next Pixel
MSB Data Out (8 Upper Bits)
↑ LSB Data Out (8 Lower Bits)
HI ADC Track PGA Output
LO ADC Hold/Convert
Table 3.
CLAMP Events
HI PGA Tracks V
CLAMP
& C
EXT
is Charged to
V
BLACK
- V
CLAMP
, which is equal to V
BLACK
LO PGA Tracks VIN
PP
Table 4.
Note: There is an 8 clock latency for the output
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

XRD9826ACD-F

Mfr. #:
Buy XRD9826ACD-F
Manufacturer:
MaxLinear
Description:
Analog to Digital Converters - ADC
Lifecycle:
New from this manufacturer.
Delivery:
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