Document Number: 38-07210 Rev. *I Page 3 of 17
Pinouts
Figure 1. Pin Diagram - 8 Pin Top View
Functional Description
CY2077 is an EPROM-programmable, high-accuracy,
general-purpose, PLL-based design for use in applications such
as modems, disk drives, CD-ROM drives, video CD players,
DVD players, games, set-top boxes, and
data/telecommunications.
CY2077 can generate a clock output up to 133 MHz at 5 V or 100
MHz at 3.3 V. It has been designed to give the customer a very
accurate and stable clock frequency with little to zero PPM error.
CY2077 contains a 12-bit feedback counter divider and 10-bit
reference counter divider to obtain a very high resolution to meet
the needs of stringent design specifications. Furthermore, there
are eight output divide options of /1, /2, /4, /8, /16, /32, /64, and
/128. The output divider can select between the PLL and crystal
oscillator output/external clock, providing a total of 16 different
options to add more flexibility in designs. TTL or CMOS duty
cycles can be selected.
Power management with the CY2077 is also very flexible. The
user can choose either a PWR_DWN, or an OE feature with
which both have integrated pull up resistors. PWR_DWN and OE
signals can be programmed to have asynchronous and
synchronous timing with respect to the output signal. There is a
weak pull down on the output that pulls CLKOUT LOW when
either the PWR_DWN or OE signal is LOW. This weak pull down
can easily be overridden by another clock signal in designs
where multiple clock signals share a signal path.
Multiple options for output selection, better power distribution
layout, and controlled rise and fall times enable the CY2077 to
be used in applications that require low jitter and accurate
reference frequencies.
EPROM Configuration Block
Table 2. EPROM Adjustable Features
PLL Output Frequency
CY2077 contains a high-resolution PLL with 12-bit multiplier and
10-bit divider.
[2]
The output frequency of the PLL is determined
by the following formula:
where P is the feedback counter value and Q is the reference
counter value. P and Q are EPROM programmable values.
The calculation of P and Q values for a given PLL output
frequency is handled by the CyberClocks software. Refer to
““Programming Procedures” on page 13” for details.
1
2
3
4
5
8
7
6
V
DD
XTALOUT
XTALIN
PD/OE
V
SS
CLKOUT
V
SS
V
SS
Table 1. Pin Definition - 8 Pin
Pin Name Pin # Pin Description
V
DD
1 Voltage supply
V
SS
5,6,7 Ground (all the pins must be grounded)
X
D
2 Crystal output (leave this pin floating when external reference is used)
X
G
3 Crystal input or external input reference
PWR_DWN / OE 4 EPROM programmable power down or output enable pin. PWR_DWN is active low. OE
is active high. Weak pull up.
CLKOUT 8 Clock output. Weak pull down
EPROM Adjustable Features
Adjust
Freq.
Feedback counter value (P)
Reference counter value (Q)
Output divider selection
Duty cycle levels (TTL or CMOS)
Power management mode (OE or PWR_DWN)
Power management timing (synchronous or asynchronous)
F
PLL
2P5+
Q2+
---------------------------
F
REF
=
Note
2. When using CyClocks, note that the PLL frequency range is from 50 MHz to 250 MHz for 5 V V
DD
supply, and 50 MHz to 180 MHz for 3 V V
DD
supply. The output
frequency is determined by the selected output divider.
