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CY2077FZZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
CY2077
Document Number: 38-07210 Rev. *I Page 10 of 17
Typical Rise/Fall Time
[8]
Trends for CY2077
Figure 7. Rise/Fall Time vs. VDD over Temperatures
Figure 8. Rise/Fall Time vs. Output Loads over Temperatures
Rise Time vs. VDD -- CMOS duty Cycle
Cload = 15pF
1.00
1.20
1.40
1.60
1.80
2.00
2.7 3.0 3.3 3.6 3.9
VDD (V)
Rise Time (ns)
-40C
25C
85C
Fall Time vs. VDD -- CMOS duty Cycle
Cload = 15pF
1.00
1.20
1.40
1.60
1.80
2.00
2.7 3.0 3.3 3.6 3.9
VDD (V)
Fall Time (ns)
-40C
25C
85C
Rise Time vs. VDD -- TTL duty Cycle
Cload = 15pF
0.20
0.30
0.40
0.50
0.60
0.70
4.0 4.5 5.0 5.5 6.0
VDD (V)
Rise Time (ns)
-40C
25C
85C
Fall Time vs. VDD -- TTL duty Cycle
Cload = 15pF
0.20
0.30
0.40
0.50
0.60
0.70
4.0 4.5 5.0 5.5 6.0
VDD (V)
Fall Time (ns)
-40C
25C
85C
Rise Time vs. CLoad over Temperature
VDD = 3.3v, CMOS output
1.00
1.50
2.00
2.50
10 15 20 25 30 35
Cload (pF)
Rise Time (ns)
-40C
25C
85C
Fall Time vs. CLoad over Temperature
VDD = 3.3v, CMOS output
1.00
1.50
2.00
10 15 20 25 30 35
Cload (pF)
Fall Time (ns)
-40C
25C
85C
Note
8. Rise/Fall time for CMOS output is measured between 1.2 V
DD
and 0.8 V
DD
. Rise/Fall time for TTL output is measured between 0.8 V and 2.0 V.
CY2077
Document Number: 38-07210 Rev. *I Page 11 of 17
Typical Duty Cycle
[9]
Trends for CY2077
Figure 9. Duty Cycle vs. V
DD
over Temperatures
Figure 10. Duty Cycle vs. Output Load
Figure 11. Duty Cycle vs. Output Frequency over Temperatures
Duty Cycle vs. VDD over Temperature
(TTL Duty Cycle Output, Fout=50MHz, Cload =
50pF)
45.00
47.00
49.00
51.00
53.00
55.00
4.0 4.5 5.0 5.5 6.0
VDD (V)
Duty Cycle (%)
-40C
25C
85C
Duty Cycle vs. VDD over Temperature
(CMOS Duty Cycle Ouput, Fout=50MHz,
Cload=50pF)
45.00
47.00
49.00
51.00
53.00
55.00
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (v)
Duty Cycle (%)
-40C
25C
85C
Duty Cycle vs. CLoad with Various VDD
(Fout = 50MHz, Temp = 25C)
45.00
47.00
49.00
51.00
53.00
55.00
10 15 20 25 30 35 40 45 50 55
Cload (pF)
Duty Cycle (%)
VDD=4.5V
VDD=5.0V
VDD=5.5V
Output Duty Cycle vs. Fout over Temperature
(Vdd = 5V, Cload = 15pF)
50.00%
51.00%
52.00%
53.00%
54.00%
55.00%
20 30 40 50 60 70 80
Output Frequency (MHz)
Output DC (%)
25C
85C
-40C
Note
9. Duty cycle is measured at 1.4 V for TTL output and 0.5 V
DD
for CMOS output.
CY2077
Document Number: 38-07210 Rev. *I Page 12 of 17
Typical Jitter Trends for CY2077
Figure 12. Period Jitter (pk-pk) vs. V
DD
over Temperatures
Figure 13. Period Jitter (pk-pk) vs. Output Frequency over Temperatures
Period Jitter (pk-pk) vs. VDD over Temperatures
(Fout=40MHz, Cload = 30pF)
0
20
40
60
80
100
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
Period JItter (ps)
-40C
25C
85C
Output Jitter (pk-pk) vs. Output Frequency
(VDD=3.3V, Cload=15pf, CMOS output)
0
20
40
60
80
10 0
020406080100120140
Output frequency (MHz)
Jitter (ps)
25C
-40C
85C
Output Jitter(pk-pk) vs. Output Frequency
(VDD=5.0V, Cload=15pf, CMOS output)
0
20
40
60
80
10 0
0 20406080100120140
Output frequency (MHz)
Jitter (ps)
25C
-40C
85C
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

CY2077FZZ

Mfr. #:
Buy CY2077FZZ
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL 1-PLL Clk Syn COM
Lifecycle:
New from this manufacturer.
Delivery:
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