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CY2077FZZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
CY2077
Document Number: 38-07210 Rev. *I Page 4 of 17
Power Management Features
PWR_DWN and OE options are configurable by EPROM
programming for the CY2077. In PWR_DWN mode, all active
circuits are powered down when the control pin is set LOW.
When the control pin is set back HIGH, both the PLL and
oscillator circuit must relock. In the case of OE, the output is
three-stated and weakly pulled down when the control pin is set
LOW. The oscillator and PLL are still active in this state, which
leads to a quick clock output return when the control pin is set
back HIGH.
Additionally, PWR_DWN and OE can be configured to occur
asynchronously or synchronously with respect to CLKOUT. In
asynchronous mode, PWR_DWN or OE disables CLKOUT
immediately (allowing for logic delays), without respect to the
current state of CLKOUT. Synchronous mode prevents output
glitches by waiting for the next falling edge of CLKOUT after
PWR_DWN, or OE becomes asserted. In either asynchronous
or synchronous setting, the output is always enabled
synchronously by waiting for the next falling edge of CLKOUT.
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply voltage.................................................–0.5 to +7.0 V
Input voltage......................................... –0.5 V to V
DD
+0.5 V
Storage temperature (non-condensing)...... –55°C to +150°C
Junction temperature.................................................. 150°C
Static discharge voltage.......................................... >
2000 V
(per MIL-STD-883, method 3015)
Operating Conditions for Commercial Temperature Device
Table 3. Device Functionality: Output Frequencies
Symbol Description Condition Min Max Unit
Fo Output frequency V
DD
= 4.5–5.5 V 0.39 133 MHz
V
DD
= 3.0–3.6 V 0.39 100 MHz
Parameter Description Min Max Unit
V
DD
Supply voltage 3.0 5.5 V
T
A
Operating temperature, ambient 0 +70 °C
C
TTL
Max. capacitive load on outputs for TTL levels
V
DD
= 4.5 – 5.5 V, output frequency = 1 – 40 MHz
V
DD
= 4.5 – 5.5 V, output frequency = 40 – 125 MHz
V
DD
= 4.5 – 5.5 V, output frequency = 125 – 133 MHz
–
–
–
50
25
15
pF
pF
pF
C
CMOS
Max. capacitive load on outputs for CMOS levels
V
DD
= 4.5 – 5.5 V, output frequency = 1 – 40 MHz
V
DD
= 4.5 – 5.5 V, output frequency = 40 – 125 MHz
V
DD
= 4.5 – 5.5 V, output frequency = 125 – 133 MHz
V
DD
= 3.0 – 3.6 V, output frequency = 1 – 40 MHz
V
DD
= 3.0 – 3.6 V, output frequency = 40 – 100 MHz
–
–
–
–
–
50
25
15
30
15
pF
pF
pF
pF
pF
X
REF
Reference frequency, input crystal with C
load
= 10 pF 10 30 MHz
Reference frequency, external clock source 1 75 MHz
t
PU
Power up time for all VDD's to reach minimum specified voltage (power
ramps must be monotonic) 0.05 50 ms
CY2077
Document Number: 38-07210 Rev. *I Page 5 of 17
Electrical Characteristics
T
A
= 0°C to +70°C
Parameter Description Test Conditions Min Typ Max Unit
V
IL
Low-level input voltage V
DD
= 4.5 – 5.5 V
V
DD
= 3.0 – 3.6 V
–
–
–
–
0.8
0.2 V
DD
V
V
V
IH
High-level input voltage V
DD
= 4.5 – 5.5 V
V
DD
= 3.0 – 3.6 V
2.0
0.7 V
DD
–
–
–
–
V
V
V
OL
Low-level output voltage V
DD
= 4.5 – 5.5 V, I
OL
= 16 mA
V
DD
= 3.0 – 3.6 V, I
OL
= 8 mA
–
–
–
–
0.4
0.4
V
V
V
OHCMOS
High-level output voltage CMOS levels V
DD
= 4.5 – 5.5 V, I
OH
= –16 mA
V
DD
= 3.0 – 3.6 V, I
OH
= –8 mA
V
DD
– 0.4
V
DD
– 0.4
–
–
–
–
V
V
V
OHTTL
High-level output voltage TTL levels V
DD
= 4.5 – 5.5 V, I
OH
= –8 mA 2.4 – – V
I
IL
Input low current V
IN
= 0 V – – 10 A
I
IH
Input high current V
IN
= V
DD
––5A
I
DD
Power supply current Unloaded V
DD
= 4.5 – 5.5 V, output
frequency <= 133 MHz
V
DD
= 3.0 – 3.6 V, output
frequency <= 100 MHz
–
–
–
–
45
25
mA
mA
I
DDS
[3]
Stand-by current (PD = 0) V
DD
= 4.5 – 5.5 V
V
DD
= 3.0 – 3.6 V
–
–
25
10
100
50
A
A
R
UP
Input pull up resistor V
DD
= 4.5 – 5.5 V, V
IN
= 0 V
V
DD
= 4.5 – 5.5 V, V
IN
= 0.7 V
DD
1.1
50
3.0
100
8.0
200
M
k
I
OE_CLKOUT
CLKOUT pull down current V
DD
= 5.0 – 20 – A
Note
3. If external reference is used, it is required to stop the reference (set reference to LOW) during power down.
CY2077
Document Number: 38-07210 Rev. *I Page 6 of 17
Output Clock Switching Characteristics Commercial
Over the Operating Range
[4]
Parameter Description Test Conditions Min Typ Max Unit
t
1w
Output duty cycle at 1.4 V,
V
DD
= 4.5 – 5.5 V
t
1w
= t
1A
t
1B
1 – 40 MHz, C
L
<= 50 pF
40 – 125 MHz, C
L
<= 25 pF
125 – 133 MHz, C
L
<= 15 pF
45
45
45
–
–
–
55
55
55
%
%
%
t
1x
Output duty cycle at V
DD
/2,
V
DD
= 4.5 – 5.5 V
t
1x
= t
1A
t
1B
1 – 40 MHz, C
L
<= 50 pF
40 – 125 MHz, C
L
<= 25 pF
125 – 133 MHz, C
L
<= 15 pF
45
45
45
–
–
–
55
55
55
%
%
%
t
1y
Output duty cycle at V
DD
/2,
V
DD
= 3.0 – 3.6 V
t
1y
= t
1A
t
1B
1 – 40 MHz, C
L
<= 30 pF
40 – 100 MHz, C
L
<= 15 pF
45
40
–
–
55
60
%
%
t
2
Output clock rise time Between 0.8 – 2.0 V, V
DD
= 4.5 V – 5.5 V, C
L
= 50 pF
Between 0.8 – 2.0 V, V
DD
= 4.5 V – 5.5 V, C
L
= 25 pF
Between 0.8 – 2.0 V, V
DD
= 4.5 V – 5.5 V, C
L
= 15 pF
Between 0.2 V
DD
– 0.8 V
DD
, V
DD
= 4.5 V – 5.5 V, C
L
= 50 pF
Between 0.2 V
DD
– 0.8 V
DD
, V
DD
= 3.0 V – 3.6 V, C
L
= 30 pF
Between 0.2 V
DD
– 0.8 V
DD
, V
DD
= 3.0 V – 3.6 V, C
L
= 15 pF
–
–
–
–
–
–
–
–
–
–
–
–
1.8
1.2
0.9
3.4
4.0
2.4
ns
ns
ns
ns
ns
ns
t
3
Output clock fall time Between 0.8 V –2.0 V, V
DD
= 4.5 V – 5.5 V, C
L
= 50 pF
Between 0.8 – 2.0 V, V
DD
= 4.5 V – 5.5 V, C
L
= 25 pF
Between 0.8 – 2.0 V, V
DD
= 4.5 V – 5.5 V, C
L
= 15 pF
Between 0.2 V
DD
– 0.8 V
DD
, V
DD
= 4.5 V – 5.5 V, C
L
= 50 pF
Between 0.2 V
DD
– 0.8 V
DD
, V
DD
= 3.0 V – 3.6 V, C
L
= 30 pF
Between 0.2 V
DD
– 0.8 V
DD
, V
DD
= 3.0 V – 3.6 V, C
L
= 15 pF
–
–
–
–
–
–
–
–
–
–
–
–
1.8
1.2
0.9
3.4
4.0
2.4
ns
ns
ns
ns
ns
ns
t
4
Startup time out of power
down
PWR_DWN pin LOW to HIGH
[5]
–12ms
t
5a
Power down delay time
(synchronous setting)
PWR_DWN pin LOW to output LOW
(T= period of output CLK)
–T/2T + 10ns
t
5b
Power down delay time
(asynchronous setting)
PWR_DWN pin LOW to output LOW – 10 15 ns
t
6
Power up time From power on
[5]
–12ms
t
7a
Output disable time
(synchronous setting)
OE pin LOW to output high-Z
(T= period of output CLK)
–T/2T + 10ns
t
7b
Output disable time
(asynchronous setting)
OE pin LOW to output high-Z – 10 15 ns
t
8
Output enable time
(always synchronous
enable)
OE pin LOW to HIGH
(T= period of output CLK)
– T 1.5T+
25ns
ns
t
9
Peak-to-peak period jitter V
DD
= 3.0 V – 3.6 V, 4.5 V – 5.5 V, Fo > 33 MHz, V
CO
> 100 MHz
V
DD
= 3.0 V – 5.5 V, Fo < 33 MHz
–
–
80
0.3%
150
1%
ps
% of
F
O
Notes
4. Not all parameters measured in production testing.
5. Oscillator start time can not be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

CY2077FZZ

Mfr. #:
Buy CY2077FZZ
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL 1-PLL Clk Syn COM
Lifecycle:
New from this manufacturer.
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