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CY2077FZZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
CY2077
Document Number: 38-07210 Rev. *I Page 7 of 17
Operating Conditions for Industrial Temperature Device
Electrical Characteristics
T
A
= –40°C to +85°C
Parameter Description Min Max Unit
V
DD
Supply voltage 3.0 5.5 V
T
A
Operating temperature, ambient –40 +85 °C
C
TTL
Max. capacitive load on outputs for TTL levels
V
DD
= 4.5 – 5.5 V, output frequency = 1 – 40 MHz
V
DD
= 4.5 – 5.5 V, output frequency = 40 – 125 MHz
V
DD
= 4.5 – 5.5 V, output frequency = 125 – 133 MHz
–
–
–
35
15
10
pF
pF
pF
C
CMOS
Max. capacitive load on outputs for CMOS levels
V
DD
= 4.5 – 5.5 V, output frequency = 1 – 40 MHz
V
DD
= 4.5 – 5.5 V, output frequency = 40 – 125 MHz
V
DD
= 4.5 – 5.5 V, output frequency = 125 – 133 MHz
V
DD
= 3.0 – 3.6 V, output frequency = 1 – 40 MHz
V
DD
= 3.0 – 3.6 V, output frequency = 40 – 100 MHz
–
–
–
–
–
35
15
10
20
10
pF
pF
pF
pF
pF
X
REF
Reference frequency, input crystal with C
load
= 10 pF 10 30 MHz
Reference frequency, external clock source 1 75 MHz
t
PU
Power up time for all VDD's to reach minimum specified voltage
(power ramps must be monotonic) 0.05 50 ms
Parameter Description Test Conditions Min Typ Max Unit
V
IL
Low-level input voltage V
DD
= 4.5 – 5.5 V
V
DD
= 3.0 – 3.6 V
–
–
–
–
0.8
0.2 V
DD
V
V
V
IH
High-level input voltage V
DD
= 4.5 – 5.5 V
V
DD
= 3.0 – 3.6 V
2.0
0.7 V
DD
–
–
–
–
V
V
V
OL
Low-level output voltage V
DD
= 4.5 – 5.5 V, I
OL
= 16 mA
V
DD
= 3.0 – 3.6 V, I
OL
= 8 mA
–
–
–
–
0.4
0.4
V
V
V
OHCMOS
High-level output voltage,
CMOS levels
V
DD
= 4.5 – 5.5 V, I
OH
= –16 mA
V
DD
= 3.0 – 3.6 V, I
OH
= –8 mA
V
DD
– 0.4
V
DD
– 0.4
–
–
–
–
V
V
V
OHTTL
High-level output voltage,
TTL levels
V
DD
= 4.5 – 5.5 V, I
OH
= –8 mA 2.4 – – V
I
IL
Input low current V
IN
= 0 V – – 10 A
I
IH
Input high current V
IN
= V
DD
––5A
I
DD
Power supply current,
Unloaded
V
DD
= 4.5 – 5.5 V, output frequency <= 133
MHz
V
DD
= 3.0 – 3.6 V, output frequency <= 100
MHz
–
–
–
–
45
25
mA
mA
I
DDS
[3]
Stand-by current
(PD = 0)
V
DD
= 4.5 – 5.5 V
V
DD
= 3.0 – 3.6 V
–
–
25
10
100
50
A
R
UP
Input pull up resistor V
DD
= 4.5 – 5.5 V, V
IN
= 0 V
V
DD
= 4.5 – 5.5 V, V
IN
= 0.7 V
DD
1.1
50
3.0
100
8.0
200
M
k
I
OE_CLKOUT
CLKOUT pull down current V
DD
= 5.0 – 20 – A
CY2077
Document Number: 38-07210 Rev. *I Page 8 of 17
Output Clock Switching Characteristics Industrial
Over the Operating Range
[4]
Parameter Description Test Conditions Min Typ. Max Unit
t
1w
Output duty cycle at 1.4
V, V
DD
= 4.5 – 5.5 V
t
1w
= t
1A
t
1B
1 – 40 MHz, C
L
<= 35 pF
40 – 125 MHz, C
L
<= 15 pF
125 – 133 MHz, C
L
<= 10 pF
45
45
45
55
55
55
%
%
%
t
1x
Output duty cycle at
V
DD
/2, V
DD
= 4.5 – 5.5 V
t
1x
= t
1A
t
1B
1 – 40 MHz, C
L
<= 35 pF
40 – 125 MHz, C
L
<= 15 pF
125 – 133 MHz, C
L
<= 10 pF
45
45
45
55
55
55
%
%
%
t
1y
Output duty cycle at
V
DD
/2, V
DD
= 3.0 – 3.6 V
t
1y
= t
1A
t
1B
1– 40 MHz, C
L
<= 20 pF
40 – 100 MHz, C
L
<= 10 pF
45
40
55
60
%
%
t
2
Output clock rise time Between 0.8 – 2.0 V, V
DD
= 4.5 V – 5.5 V, C
L
= 35 pF
Between 0.8 – 2.0 V, V
DD
= 4.5 V – 5.5 V, C
L
= 15 pF
Between 0.8 – 2.0 V, V
DD
= 4.5 V – 5.5 V, C
L
= 10 pF
Between 0.2 V
DD
– 0.8 V
DD
, V
DD
= 4.5 V – 5.5 V, C
L
= 35 pF
Between 0.2 V
DD
– 0.8 V
DD
, V
DD
= 3.0 V – 3.6 V, C
L
= 20 pF
Between 0.2 V
DD
– 0.8 V
DD
, V
DD
= 3.0 V – 3.6 V, C
L
= 10 pF
–
–
–
–
–
–
1.8
1.2
0.9
3.4
4.0
2.4
ns
ns
ns
ns
ns
ns
t
3
Output clock fall time Between 0.8 V – 2.0 V, V
DD
= 4.5 V – 5.5 V, C
L
= 35 pF
Between 0.8 – 2.0 V, V
DD
= 4.5 V – 5.5 V, C
L
= 15 pF
Between 0.8 – 2.0 V, V
DD
= 4.5 V – 5.5 V, C
L
= 10 pF
Between 0.2 V
DD
– 0.8 V
DD
, V
DD
= 4.5 V – 5.5 V, C
L
= 35 pF
Between 0.2 V
DD
– 0.8 V
DD
, V
DD
= 3.0 V – 3.6 V, C
L
= 20 pF
Between 0.2 V
DD
– 0.8 V
DD
, V
DD
= 3.0 V – 3.6 V, C
L
= 10 pF
–
–
–
–
–
–
1.8
1.2
0.9
3.4
4.0
2.4
ns
ns
ns
ns
ns
ns
t
4
Startup time out of Power
down
PWR_DWN pin LOW to HIGH
[5]
–12ms
t
5a
Power down delay time
(synchronous setting)
PWR_DWN pin LOW to output LOW
(T= period of output clk)
– T/2 T+10 ns
t
5b
Power down delay time
(asynchronous setting)
PWR_DWN pin LOW to output LOW – 10 15 ns
t
6
Power up time From power on
[5]
–12ms
t
7a
Output Disable time
(synchronous setting)
OE pin LOW to output high-Z
(T= period of output clk)
– T/2 T + 10 ns
t
7b
Output Disable time
(asynchronous setting)
OE pin LOW to output high-Z – 10 15 ns
t
8
Output Enable time
(always synchronous
enable)
OE pin LOW to HIGH
(T = period of output clk)
–T1.5T +
25ns
ns
t
9
Peak-to-peak period
jitter
V
DD
= 3.0 V – 3.6 V, 4.5 V – 5.5 V, Fo > 33 MHz, V
CO
> 100
MHz
V
DD
= 3.0 V – 5.5 V, Fo < 33 MHz
–
–
80
0.3%
150
1%
ps
% of F
O
CY2077
Document Number: 38-07210 Rev. *I Page 9 of 17
Switching Waveforms
Figure 2. Duty Cycle Timing (t
1w
, t
1x
, t
1y
)
Figure 3. Output Rise/Fall Time
Figure 4. Power down Timing (synchronous and asynchronous modes)
Figure 5. Power up Timing
Figure 6. Output Enable Timing (synchronous and asynchronous modes)
Notes
6. In synchronous mode, the power down or output three-state is not initiated until the next falling edge of the output clock.
7. In asynchronous mode, the power down or output three-state occurs within 25 ns regardless of position in the output clock cycle.
t
1A
t
1B
OUTPUT
OUTPUT
t
2
V
DD
0 V
t
3
CLKOUT
VDD
t4
1/f
t5a
VIL
VIH
POWER
DOWN
0 V
1/f
t5b
CLKOUT
T
(synchronous
[
6]
)
(asynchronous
[
7]
)
CLKOUT
V
DD
t6
1/f
V
DD
– 10%
POWER
UP
0 V
min 30 s
max 30 ms
CLKOUT
V
DD
OUTPUT
ENABLE
0 V
VIL
t7a
t8
High Impedance
CLKOUT
t7b
t8
High Impedance
T
(synchronous
[
6]
)
(asynchronous
[
7]
)
VIH
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

CY2077FZZ

Mfr. #:
Buy CY2077FZZ
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL 1-PLL Clk Syn COM
Lifecycle:
New from this manufacturer.
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