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ADG3308BCPZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
Low Voltage, 1.15 V to 5.5 V, 8-Channel
Bidirectional Logic Level Translators
Data Sheet
ADG3308/ADG3308-1
Rev. E Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Bidirectional logic level translation
Operates from 1.15 V to 5.5 V
Low quiescent current < 1 μA
No direction pin
APPLICATIONS
Low voltage ASIC level translation
Smart card readers
Cell phones and cell phone cradles
Portable communication devices
Telecommunications equipment
Network switches and routers
Storage systems (SAN/NAS)
Computing/server applications
GPS
Portable POS systems
Low cost serial interfaces
FUNCTIONAL BLOCK DIAGRAM
A1
Y1
GND
V
CCY
V
CCA
A8
Y8
A7
Y7
A6
Y6
A5
Y5
A4 Y4
A3
Y3
A2
Y2
EN
ADG3308/ADG3308-1
0
4865-001
Figure 1.
GENERAL DESCRIPTION
The ADG3308/ADG3308-1 are bidirectional level translators
containing eight bidirectional channels. They can be used in
multivoltage digital system applications, such as a data transfer
between a low voltage DSP controller and a higher voltage device.
The internal architecture allows the device to perform
bidirectional level translation without an additional signal to set
the direction in which the translation takes place.
The voltage applied to V
CCA
sets the logic levels on the A side
of the device, and V
CCY
sets the levels on the Y side. For proper
operation, V
CCA
must always be less than V
CCY
. The V
CCA
compatible logic signals applied to the A side of the device
appear as V
CCY
compatible levels on the Y side. Similarly, V
CCY
compatible logic levels applied to the Y side of the device appear
as V
CCA
compatible logic levels on the A side.
The enable pin (EN) provides three-state operation on both the
A side and the Y side pins. When the EN pin is pulled low, the
terminals on both sides of the device are in the high impedance
state. For normal operation, EN should be driven high.
The ADG3308 is available in a compact 20-lead TSSOP and
a 20-lead LFCSP. The ADG3308-1 is available in a 20-ball
WLCSP. The EN pin is referred to the V
CCY
supply voltage
for the ADG3308 and to the V
CCA
supply voltage for the
ADG3308-1.
The ADG3308/ADG3308-1 are guaranteed to operate over the
1.15 V to 5.5 V supply voltage range and the extended −40°C to
+85°C temperature range.
PRODUCT HIGHLIGHTS
1. Bidirectional logic level translation.
2. Fully guaranteed over the 1.15 V to 5.5 V supply range.
3. No direction pin.
4. Packages: 20-lead TSSOP and 20-lead LFCSP (ADG3308)
and 20-ball WLCSP (ADG3308-1).
ADG3308/ADG3308-1 Data Sheet
Rev. E | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Test Circuits ..................................................................................... 12
Terminology .................................................................................... 15
Theory of Operation ...................................................................... 16
Level Translator Architecture ................................................... 16
Input Driving Requirements ..................................................... 16
Output Load Requirements ...................................................... 16
Enable Operation ....................................................................... 16
Power Supplies ............................................................................ 16
Data Rate ..................................................................................... 17
Applications ..................................................................................... 18
Layout Guidelines....................................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
3/16—Rev. D to Rev. E
Changed CP-20-1 to CP-20-6 ...................................... Throughout
Changes to Figure 3 .......................................................................... 7
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
10/13—Rev. C to Rev. D
Removed ADG3308-2 (Throughout) ............................................ 1
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
9/07—Rev. B to Rev. C
Updated Outline Dimensions ....................................................... 19
7/07—Rev. A to Rev. B
Added Backside-Coated WLCSP Package ...................... Universal
Changes to Input Driving Requirements Section ...................... 16
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
7/06—Rev. 0 to Rev. A
Added WLCSP Package…………………………..……Universal
Added Figure 4………………………………………………......7
Updated Outline Dimensions……………………………….…19
Changes to Ordering Guide………………………………....…19
1/05—Revision 0: Initial Version
Data Sheet ADG3308/ADG3308-1
Rev. E | Page 3 of 20
SPECIFICATIONS
V
CCY
= 1.65 V to 5.5 V, V
CCA
= 1.15 V to V
CCY
, GND = 0 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
1
Table 1.
Parameter Symbol Conditions Min Typ
2
Max Unit
LOGIC INPUTS/OUTPUTS
A Side
Input High Voltage
3
V
IHA
V
CCA
= 1.15 V V
CCA
− 0.3 V
V
IHA
V
CCA
= 1.2 V to 5.5 V 0.65 × V
CCA
V
Input Low Voltage
3
V
ILA
0.35 × V
CCA
V
Output High Voltage V
OHA
V
Y
= V
CCY
, I
OH
= 20 μA, see Figure 29 V
CCA
− 0.4 V
Output Low Voltage V
OLA
V
Y
= 0 V, I
OL
= 20 μA, see Figure 29 0.4 V
Capacitance
3
C
A
f = 1 MHz, EN = 0, see Figure 34 10 pF
Leakage Current I
LA, HIGH-Z
V
A
= 0 V or V
CCA
, EN = 0, see Figure 31 ±1 μA
Y Side
Input High Voltage
3
V
IHY
0.65 × V
CCY
V
Input Low Voltage
3
V
ILY
0.35 × V
CCY
V
Output High Voltage V
OHY
V
A
= V
CCA
, I
OH
= 20 μA, see Figure 30 V
CCY
− 0.4 V
Output Low Voltage V
OLY
V
A
= 0 V, I
OL
= 20 μA, see Figure 30 0.4 V
Capacitance
3
C
Y
f = 1 MHz, EN = 0, see Figure 35 6.8 pF
Leakage Current I
LY, H IG H- Z
V
Y
= 0 V or V
CCY
, EN = 0, see Figure 32 ±1 μA
Enable (EN)
Input High Voltage
3
V
IHEN
ADG3308 (TSSOP, LFCSP)
0.65 × V
CCY
V
ADG3308-1 (WLCSP) V
CCA
= 1.15 V V
CCA
− 0.3 V
V
CCA
= 1.2 V to 5.5 V 0.65 × V
CCA
V
Input Low Voltage
3
V
ILEN
ADG3308 (TSSOP, LFCSP)
0.35 × V
CCY
V
ADG3308-1 (WLCSP) 0.35 × V
CCA
V
Leakage Current I
LEN
V
EN
= 0 V or V
CCY
, V
A
= 0 V, see Figure 33 ±1 μA
Capacitance
3
C
EN
4.5 pF
Enable Time
3
t
EN
R
S
= R
T
= 50 Ω, V
A
= 0 V or
V
CCA
(A→Y), V
Y
= 0 V or V
CCY
(Y→A),
see Figure 36
1 1.8 μs
SWITCHING CHARACTERISTICS
3
3.3 V ± 0.3 V ≤ V
CCA
≤ V
CCY
, V
CCY
= 5 V ± 0.5 V
A→Y Level Translation
R
S
= R
T
= 50 Ω, C
L
= 50 pF, see Figure 37
Propagation Delay
t
P, A →Y
6 10 ns
Rise Time
t
R, A→Y
2 3.5 ns
Fall Time
t
F, A →Y
2 3.5 ns
Maximum Data Rate
D
MAX, A→Y
50 Mbps
Channel-to-Channel Skew
t
SKEW, A→Y
2 4 ns
Part-to-Part Skew
t
PPSKEW, A→Y
3 ns
Y→A Level Translation
R
S
= R
T
= 50 Ω, C
L
= 15 pF, see Figure 38
Propagation Delay
t
P, Y →A
4 7 ns
Rise Time
t
R, Y→A
1 3 ns
Fall Time
t
F, Y →A
3 7 ns
Maximum Data Rate
D
MAX, Y→A
50 Mbps
Channel-to-Channel Skew
t
SKEW, Y→A
2 3.5 ns
Part-to-Part Skew
t
PPSKEW, Y→A
2 ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

ADG3308BCPZ-REEL7

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Translation - Voltage Levels Low VTG 1.15V-5.5V 8-CH Bidirect Logic
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