ADG3308/ADG3308-1 Data Sheet
Rev. E | Page 16 of 20
THEORY OF OPERATION
The ADG3308/ADG3308-1 level translators allow the level
shifting necessary for data transfer in a system where multiple
supply voltages are used. The device requires two supplies, V
CCA
and V
CCY
(V
CCA
≤ V
CCY
). These supplies set the logic levels on
each side of the device. When driving the A pins, the device
translates the V
CCA
compatible logic levels to V
CCY
compatible
logic levels available at the Y pins. Similarly, because the device
is capable of bidirectional translation, when driving the Y pins
the V
CCY
compatible logic levels are translated to the V
CCA
compatible logic levels available at the A pins. When EN = 0,
the A1 pin to the A8 pin and the Y1 pin to the Y8 pin are three-
stated. When EN is driven high, the ADG3308/ADG3308-1 go
into normal operation mode and perform level translation.
LEVEL TRANSLATOR ARCHITECTURE
The ADG3308/ADG3308-1 consist of eight bidirectional
channels. Each channel can translate logic levels in either the
A→Y or the Y→A direction. They use a one-shot accelerator
architecture, ensuring excellent switching characteristics.
Figure 39 shows a simplified block diagram of a bidirectional
channel.
ONE-SHOT GENERATOR
6kΩ
6kΩ
Y
CCA
CCY
T2T1
T3T4
A
P
N
U1
U2
U4
U3
4865-053
Figure 39. Simplified Block Diagram of an
ADG3308/ADG3308-1 Channel
The logic level translation in the A→Y direction is performed
using a level translator (U1) and an inverter (U2), whereas the
translation in the Y→A direction is performed using the U3
inverter and U4 inverter. The one-shot generator detects a rising
or falling edge present on either the A side or the Y side of the
channel. It sends a short pulse that turns on the PMOS transistors
(T1 and T2) for a rising edge, or the NMOS transistors (T3 and
T4) for a falling edge. This charges/discharges the capacitive load
faster, resulting in fast rise and fall times.
The inputs of the unused channels (A or Y) should be tied to
their corresponding V
CC
rail (V
CCA
or V
CCY
) or to GND.
INPUT DRIVING REQUIREMENTS
To ensure correct operation of the ADG3308/ADG3308-1,
the circuit that drives the input of the device should be able
to ensure rise/fall times of less than 3 ns when driving a
load consisting of a 6 kΩ resistor in parallel with the input
capacitance of the ADG3308/ADG3308-1 channel.
OUTPUT LOAD REQUIREMENTS
The ADG3308/ADG3308-1 level translators are designed to
drive CMOS-compatible loads. If current-driving capability
is required, it is recommended to use buffers between the
ADG3308/ADG3308-1 outputs and the load.
ENABLE OPERATION
The ADG3308/ADG3308-1 provide three-state operation at the
A I/O pins and the Y I/O pins by using the enable (EN) pin, as
shown in Table 4.
Table 4. Truth Table
EN
Y I/O Pins A I/O Pins
0 High-Z
1
High-Z
1
1 Normal operation
2
Normal operation
2
1
High impedance state.
2
In normal operation, the ADG3308/ADG3308-1 perform level translation.
When EN = 0, the ADG3308/ADG3308-1 enter into three-state
mode. In this mode, the current consumption from both the
V
CCA
and V
CCY
supplies is reduced, allowing the user to save
power, which is critical, especially in battery-operated systems.
The EN input pin can only be driven with V
CCY
compatible logic
levels for the ADG3308, whereas the ADG3308-1 can be driven
with either V
CCA
- or V
CCY
compatible logic levels.
POWER SUPPLIES
For proper operation of the device, the voltage applied to the
V
CCA
must always be less than or equal to the voltage applied
to V
CCY
. To meet this condition, the recommended power-up
sequence is V
CCY
first and then V
CCA
. The ADG3308/ADG3308-1
operate properly only after both supply voltages reach their
nominal values. It is not recommended to use the part in a system
where, during power-up, V
CCA
may be greater than V
CCY
due to
a significant increase in the current taken from the V
CCA
supply.
For optimum performance, the V
CCA
and V
CCY
pins should be
decoupled to GND as close as possible to the device.
