VCXO Jitter Attenuator and
FemtoClock™ Multiplier
ICS810252BI-03
DATA SHEET
ICS810252BYI-03 REVISION A AUGUST 20, 2009 1 ©2009 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The ICS810252BI-03 is a member of the
HiperClockS family of high performance clock
solutions from IDT. The ICS810252BI-03 is a PLL
based synchronous multiplier that is optimized for
PDH or SONET to Ethernet clock jitter attenuation
and frequency translation. The device contains two internal
frequency multiplication stages that are cascaded in series.
The first stage is a VCXO PLL that is optimized to provide
reference clock jitter attenuation. The second stage is a
FemtoClock frequency multiplier that provides the low jitter,
high frequency Ethernet output clock that easily meets Gigabit
and 10 Gigabit Ethernet jitter requirements. Pre-divider and
output divider multiplication ratios are selected using device
selection control pins. The multiplication ratios are optimized
to support most common clock rates used in PDH, SONET
and Ethernet applications. The VCXO requires the use of an
external, inexpensive pullable crystal. The VCXO uses external
passive loop filter components which allows configuration of
the PLL loop bandwidth and damping characteristics. The
device is packaged in a space-saving 32-TQFP, E-Pad and 32-
VFQFN packages and supports industrial temperature range.
PIN ASSIGNMENT
HiPerClockS™
ICS
FEATURES
Two LVCMOS/LVTTL outputs, 17Ω impedance
Each output supports independent frequency selection at
25MHz, 62.5MHz, 125MHz, and 156.25MHz
Two differential inputs support the following input types:
L
VPECL, LVDS, LVHSTL, SSTL, HCSL
Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
Attenuates the phase jitter of the input clock by using a low-
cost pullab
le fundamental mode VCXO crystal
VCXO PLL bandwidth can be optimiz
ed for jitter attenuation
and reference tracking using external loop filter connection
FemtoClock frequency multiplier provides low jitter, high
frequency output
Absolute pull range: ±50ppm
F
emtoClock VCO frequency: 625MHz
RMS phase jitter @ 125MHz, using a 25MHz crystal
(12kHz - 20MHz): 1.1ps (typical)
3.3V supply v
oltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
V
DDO_QB
QB
GND
V
DDO_QA
QA
GND
ODASEL_0
ICS810252BI-03
PDSEL_2
PDSEL_1
PDSEL_0
V
DD
VDDA
ODBSEL_1
ODBSEL_0
ODASEL_1
nCLK1
CLK1
V
DD
nCLK0
CLK0
XTAL_OUT
XTAL_IN
V
DDX
LF1
LF0
ISET
GND
CLK_SEL
V
DD
RESERVED
GND
32-Lead TQFP, E-Pad
7mm x 7mm x 1.0mm package body
Y package
Top View
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
For functional replacement device use 810252DKI-02LF or
8T49N282B-dddNLGI
OBSOLETE
ICS810252BYI-03 REVISION A AUGUST 20, 2009 2 ©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
BLOCK DIAGRAM
Charge
Pump
VCXO
Phase
Detector
QA
Output
Divider
00 = 25
01 = 5
10 = 4
11 = 10
VCXO Feedback Divider
÷3125
VCXO Input
Pre-Divider
VCXO Jitter Attenuation PLL
XTAL_IN
XTAL_OUT
LF1
LF0
ISET
Loop
Filter
ODASEL_[1:0]
CLK0
PDSEL_[2:0]
nCLK0
0
1
25MHz
2
QB
Output
Divider
00 = 25
01 = 5
10 = 4
11 = 10
ODBSEL_[1:0]
2
FemtoClock PLL
625MHz
000 = 1
001 = 193
010 = 256
011 = 2430
100 = 3125
101 = 9720
110 = 15625
111 = 19440
CLK1
nCLK1
CLK_SEL
Pulldown
PU
PD
PU/PD
PD
PU/PD
PD
PD
3
ICS810252BYI-03 REVISION A AUGUST 20, 2009 3 ©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
TABLE 2. PIN CHARACTERISTICS
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R
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TABLE 1. PIN DESCRIPTIONS
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810252BYI-03LFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner ICS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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