ICS810252BYI-03 REVISION A AUGUST 20, 2009 21 ©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
TABLE 9B. PACKAGE DIMENSIONS
PACKAGE OUTLINE AND DIMENSIONS - K SUFFIX FOR 32 LEAD VFQFN
Reference Document: JEDEC Publication 95, MO-220
To p View
Index Area
D
Cham fer 4x
0.6 x 0.6 max
OPTIONAL
Anvil
Singula tion
A
0. 08 C
C
A3
A1
S eating Plan e
E2
E2
2
L
(N
-1)x e
(Ref.)
(Ref.)
N & N
Even
N
e
D2
2
D2
(Ref.)
N & N
Odd
1
2
e
2
(Ty p.)
If N & N
are Even
(N -1)x e
(Re f.)
b
Th er mal
Base
N
OR
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This draw-
ing is not intended to convey the actual pin count or pin layout of
this device. The pin count and pinout are shown on the front page.
The package dimensions are in Table 9B below.
NOITAIRAVCEDEJ
SRETEMILLIMNISNOISNEMIDLLA
LOBMYS
2-DHHV
MUMINIMLANIMONMUMIXAM
N
23
A
08.0--00.1
1A
0--50.0
3A
.feR52.0
b
81.052.003.0
N
D
8
N
E
8
D
CISAB00.5
2D
0.351.33.3
E
CISAB00.5
2E
0.351.33.3
e
CISAB05.0
L
03.004.005.0
