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810252BYI-03LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
ICS810252BYI-03 REVISION A AUGUST 20, 2009 16 ©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality
operation of the VCXO-PLL. In choosing a crystal, special
precaution must be taken with the package and load
capacitance (C
L
). In addition, frequency, accuracy and
temperature range must also be considered. Since the pulling
range of a crystal also varies with the package, it is
recommended that a metal-canned package like HC49 be
used. Generally, a metal-canned package has a larger pulling
range than a surface mounted device (SMD). For crystal
selection information, refer to the
VCXO Crystal Selection
Application Note.
The crystal’s load capacitance C
L
characteristic determines its
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance,
IC package lead capacitance, internal varactor capacitance and
any installed tuning capacitors (C
TUNE
).
If the crystal C
L
is greater than the total external capacitance,
the VCXO will oscillate at a higher frequency than the crystal
specification. If the crystal C
L
is lower than the total external
capacitance, the VCXO will oscillate at a lower frequency than
VCXO-PLL LOOP BANDWIDTH SELECTION TABLE
htdiwdnaB)zHM(ycneuqerFlatsyrCR
S
k( ΩΩ
Ω
ΩΩ)C
S
)Fµ(C
P
)Fµ(R
TES
k( ΩΩ
Ω
ΩΩ)
)woL(zH01zHM520210.110.08.8
)diM(zH05zHM521221.0100.012.2
)hgiH(zH521zHM52026220.04000.012.2
CRYSTAL CHARACTERISTICS
VCXO CHARACTERISTICS TABLE
lobmySretemaraPmuminiMlacipyTmumixaMstinU
noitarepOfoedoMlatnemadnuF
f
N
ycneuqerF52zHM
f
T
ecnareloTycneuqerF02±mpp
f
S
ytilibatSycneuqerF02±mpp
egnaRerutarepmeTgnitarepO04-58C°
C
L
ecnaticapaCdaoL01Fp
C
O
ecnaticapaCtnuhS4Fp
C
O
/C
1
oitaRytiliballuP022042
F
TV03_L
3
dr
FenotrevO
L
002
F
SRUPS_TV03_L
3
dr
FenotrevO
L
srupS002
RSEecnatsiseRseireStnelaviuqE04
Ω
leveLevirD1Wm
C°52@gnigAraeyrep3±mpp
lobmySretemaraPlacipyTtinU
k
OXCV
niaGOXCV0008V/zH
C
WOL_V
ecnaticapaCrotcaraVwoL8Fp
C
HGIH_V
ecnaticapaCrotcaraVhgiH71Fp
the crystal specification. In either case, the absolute tuning
range is reduced. The correct value of C
L
is dependant on the
characteristics of the VCXO. The recommended C
L
in the
Crystal Parameter Table
balances the tuning range by
centering the tuning curve.
The frequency of oscillation in the third overtone mode is not
necessarily at exactly three times the fundamental frequency.
The mechanical properties of the quartz element dictate the
position of the overtones relative to the fundamental. The
oscillator circuit may excite both the fundamental and overtone
modes simultaneously. This will
cause a nonlinearity in the
tuning curve. This potential
problem is the reason VCXO
crystals are required to be
tested for absence of any
activity inside a ±200ppm
window at three times the
fundamental frequency. Refer to
F
L_30VT
and F
L_30VT_SPURS
in the Crystal
Characterization Table.
The crystal and external loop
filter components should be
kept as close as possible to the device. Loop filter and crystal
traces should be kept short and separated from each other.
Other signal traces should be kept separate and not run
underneath the device, loop filter or crystal components.
LF0
LF1
ISET
XTAL_IN
XTAL_OUT
R
S
C
S
C
P
R
SET
C
TUNE
C
TUNE
25MHz
ICS810252BYI-03 REVISION A AUGUST 20, 2009 17 ©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
This section provides information on power dissipation and junction temperature for the ICS810252BI-03.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS810252BI-03 is the sum of the core power plus the analog plus the power dissipated in the
load(s). The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
Core Power Dissipation
• Power (core)
MAX
= V
DD_MAX
* ((I
DD
+ I
DDX
) + I
DDA
) = 3.465V * (190mA + 13mA) = 703.4mW
Output Power Dissipation
• Output Impedance R
OUT
Power Dissipation due to Loading 50Ω to V
DDO
/2
Output Current I
OUT
= V
DDO_MAX
/ [2 * (50Ω + R
OUT
)] = 3.465V / [2 * (50Ω + 17Ω)] = 25.9mA
• Power Dissipation on the R
OUT
per LVCMOS output
Power (R
OUT
) = R
OUT
* (I
OUT
)
2
= 17Ω * (25.9mA)
2
= 11.4mW per output
• Total Power Dissipation on the R
OUT
Total Power (R
OUT
) = 11.4mW * 2 = 22.8mW
Dynamic Power Dissipation at 125MHz
Power (125MHz) = C
PD
* Frequency * (V
DDO
)
2
= 10pF * 125MHz * (3.465V)
2
= 15mW per output
Total Dynamic Power (125MHz) = 15mW * 2 = 30mW
Total Power Dissipation
• Total Power
= Power (core)
MAX
+ Total Power (R
OUT
) + Total Dynamic Power (125MHz)
= 703.4mW + 22.8mW + 30mW
= 756.2mW
2. Junction Temperature.
Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum
recommended junction temperature for HiPerClockS
TM
devices is 125°C. Limiting the internal transistor junction temperature, Tj, to
125°C ensures that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θ
JA
* Pd_total + T
A
Tj = Junction Temperature
θ
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 37°C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.756W * 37°C/W = 113°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of terminated outputs, supply voltage, air flow,
and the number of board layers.
TABLE 6A. THERMAL RESISTANCE
θθ
θθ
θ
JA
FOR 32 LEAD VFQFN, FORCED CONVECTION
θθ
θθ
θ
JA
vs. 0 Air Flow (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 37.0°C/W 32.4°C/W 29.0°C/W
POWER CONSIDERATIONS
TABLE 6B.
θθ
θθ
θ
JA
VS. AIR FLOW TABLE FOR 32 LEAD TQFP, E-PAD
θθ
θθ
θ
JA
by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 32.2°C/W 26.3°C/W 24.7°C/W
ICS810252BYI-03 REVISION A AUGUST 20, 2009 18 ©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
3. Case Temperature calculated from Junction Temperature
θ
JC
Calculations
In applications where there is a heatsink present, and the majority of the power is dissipated through the top of the device, the
junction temperature can be calculated from the case temperature, T
C
, using the junction-to-case thermal resistance value θ
JC
. In
practical application is it the average of the case temperature of the surface of the device on which the heatsink is attached.
The equation for calculating the junction temperature is as follows:
Tj = θ
JC
* Pd_case
+ T
C
Tj = Junction Temperature
θ
JC
= Junction-to-Case Thermal Resistance
Pd_case
= Total Device Power Dissipation
through the case
T
C
= Average Case Temperature
It is important to emphasize that case temperature calculations using θ
JC
do not use Pd_total,
rather they use Pd_case, which is the
portion of power dissipated through the case. In real applications it is difficult to quantify the power dissipated through the case, so
the value of θ
JC
is best used for a package-to-package comparison, rather than a junction temperature calculation. As such, the
JEDEC standard (JESD51-2) uses another parameter, ψ
JT
(PsiJT), which can be used to calculate junction temperature from a
measured case temperature.
ψψ
ψψ
ψ
JT
Calculations
ψ
JT
is the thermal characterization parameter which reports the differences between junction temperature and the temperature at
the top dead center of the outside surface of the component package, divided by the power applied to the component. This requires
knowing the total power dissipation and a measured case temperature in order to calculate the junction temperature. It can also be
calculated using an estimated case temperature for a given junction temperature. In the following equation, T
T
, is used to indicate
the single-point temperature measurement at the top-center of the case. The change in the naming convention from T
C
to T
T
is to
differentiate the use between the θ
JC
and ψ
JT
calculations.
The equation for T
J
is as follows: T
J
= T
T
+ ψ
JT
* Pd_total
Solving for T
T
yields: T
T
= T
J
- ψ
JT
* Pd_total
T
J
= Junction Temperature
ψ
JT
= (PsiJT) Junction-to-Top of Package Parameter
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
T
= Temperature at the top-center of the package
The advantage of this method is that it allows for the calculation of the junction temperature or case temperature using total power
dissipation and eliminates the need to quantify power dissipation through the top of the device. In order to calculate T
T,
the
appropriate ψ
JT
factor must be used. Assuming no air flow, a multi-layer board, and E-Pad soldered to the board, the appropriate
value is 0.3°C/W per Table 7 below. Therefore, T
T
for a T
J
value of 113°C (from the example in section 2) with all outputs switching
is:
T
T
= 113.0°C – 0.756W * 0.3°C/W = 112.8°C.
This calculation is only an example. T
J
will vary depending on the number of terminated outputs, supply voltage, air flow and the
number of board layers.
Table 7. ψ
JT
for 32 Lead VFQFN, Forced Convection
ψ
JT
by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 0.3°C/W
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

810252BYI-03LFT

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Clock Synthesizer / Jitter Cleaner ICS
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