ICS810252BYI-03 REVISION A AUGUST 20, 2009 13 ©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PAT H –SIDE VIEW (DRAWING NOT TO SCALE)
VFQFN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in
Figure 4.
The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”)
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the
Surface Mount Assembly
of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor
Technology.
THERMAL VIA
LAND PATTERN
SOLDER
PIN
SOLDER
PIN PADPIN PAD
PIN
GROUND PLANE
EXPOSED HEAT SLUG
(GROUND PAD)
ICS810252BYI-03 REVISION A AUGUST 20, 2009 14 ©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
FIGURE 5. ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
TQFP EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in
Figure 5.
The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”)
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the
Surface Mount Assembly
of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor
Technology.
GROUND PLANE
LAND PATTERN
SOLDER
THERMAL VIA
EXPOSED HEAT SLUG
(GROUND PAD)
PIN
PIN PAD
SOLDER
PIN
PIN PAD
SOLDER
ICS810252BYI-03 REVISION A AUGUST 20, 2009 15 ©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
FIGURE 6. SCHEMATIC OF RECOMMENDED LAYOUT
LAYOUT GUIDELINE
Figure 6
shows an example of the 810252IB-03 application
schematic. In this example, the device is operated at V
DD
= 3.3V.
The decoupling capacitors should be located as close as possible
to the power pin. The input is driven by a 3.3V LVPECL driver. An
optional 3-pole filter can also be used for additional spur reduction.
It is recommended that the loop filter components be laid out for
the 3-pole option. This will also allow the 2-pole filter to be used.
PDSEL_0
LF0
GND
R10
85
R26 10
R12
84
Zo = 50
R11
125
R1
35
LF0
Zo = 50
C46
10u
R20
2.21K
XTA L_I N
C29
3pf
VDDA
R2
35
C18
0.1u
2-pole loop filter example
LF1
Zo = 50
C28
3pf
ODBSEL_1
ODASEL_1
VDDO_QA
ODASEL_0
C47
0.01u
Rs
221k
XTA L_OU T
R25
10
Cp
0.01uF
Zo = 50
C12
0.1u
nCLK1
VDDO_QA
CLK0
Zo = 50
C15
0.1u
LF0
VDD
3-pole loop filter example - (optional)
R7
125
C14
0.1u
VDD = VDDX = VDDO_QA = VDDO_QB = 3.3V
VDD
Rs
200k
C17
0.1u
VDD
LF1
R9
125
LVPECL Driv er
R14
84
R3
820k
GND
C45
10u
Receiver
R8
84
CLK1
R13
125
LF1
C28 and C29 are used for additional capacitance
to center VCXO tuning curve. For most layouts,
it is recommended to add an additional 3pf.
For boards with high parasitics, C28 and 29
might not be required.
VDD
PDSEL_2
LF0
LF1
Cs
1.0uF
nCLK0
C30
0.01u
LVPECL Driv er
VDDO_QB
ODBSEL_0
GND
VDD
VDDX
Zo = 50
Receiver
VDDO_QB
PDSEL_1
GND
Cp
0.001uF
CLK_SEL
nCLK0
VDD
VDD
Cs
0.1uF
U1
ICS810252Bi-03
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
LF1
LF0
ISET
GND
CLK_SEL
VDD
nc
GND
PDSEL_2
PDSEL_1
PDSEL_0
VDD
VDDA
ODBSEL_1
ODBSEL_0
ODASEL_1
ODASEL_0
GND
QA
VDDO_QA
GND
QB
VDDO_QB
GND
VDDX
XTAL_IN
XTAL_OUT
CLK0
nCLK0
VDD
CLK1
nCLK1
CLK0
C3
220pF
25MHz, CL =10pf

810252BYI-03LFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner ICS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union