DS28EC20P+ Datasheet DS28EC20P+T, DS28EC20+, DS28EC20+T | P10-P12

DS28EC20: 20Kb 1-Wire EEPROM

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ADDRESS REGISTERS AND TRANSFER STATUS

The DS28EC20 employs three address registers: TA1, TA2, and E/S (Figure 6). Registers TA1 and TA2 must be

loaded with the target address to which the data is written or from which data is read. Register E/S is a read-only

transfer status register used to verify data integrity with write commands. E/S bits E[4:0] are loaded with the

incoming T[4:0] on a Write Scratchpad command and increment on each subsequent data byte. This is, in effect, a

byte-ending offset counter within the 32-byte scratchpad. Bit 5 of the E/S register, called PF, is set if the number of

data bits sent by the master is not an integer multiple of 8 or if the data in the scratchpad is not valid due to a loss

of power. A valid write to the scratchpad clears the PF bit. Bit 6 has no function; it always reads 0. The highest

valued bit of the E/S register, called authorization accepted (AA), is valid only if the PF flag reads 0. If PF is 0 and

AA is 1, the data stored in the scratchpad has already been copied to the target memory address. Writing data to

the scratchpad clears this flag.

Figure 6. Address Registers

Bit # 7 6 5 4 3 2 1 0

Target Address (TA1) T7 T6 T5 T4 T3 T2 T1 T0

Target Address (TA2) T15 T14 T13 T12 T11 T10 T9 T8

Ending Address with

Data Status (E/S)

(Read Only)

AA 0 PF E4 E3 E2 E1 E0

WRITING WITH VERIFICATION

To write data to the DS28EC20, the scratchpad must be used as intermediate storage. First, the master issues the

Write Scratchpad command to specify the desired target address, followed by the data to be written to the

scratchpad. Under certain conditions (see the Write Scratchpad Command section) the master receives an inverted

CRC16 of the command, address (actual address sent), and data at the end of the Write Scratchpad command

sequence. Knowing this CRC value, the master can compare it to the value it has calculated itself to decide if the

communication was successful and precede to the Copy Scratchpad command. If the master could not receive the

CRC16, it should send the Read Scratchpad command to verify data integrity. As a preamble to the scratchpad

data, the DS28EC20 repeats the target address TA1 and TA2 and sends the contents of the E/S register. If the PF

flag is set, data did not arrive correctly in the scratchpad or there was a loss of power since data was last written to

the scratchpad. The master does not need to continue reading; it can start a new trial to write data to the

scratchpad. Similarly, a set AA flag together with a cleared PF flag indicates that the device did not recognize the

Write command. If everything went correctly, both flags are cleared and the ending offset indicates the address of

the last byte written to the scratchpad. Now the master can continue reading and verifying every data byte. After

the master has verified the data, it can send the Copy Scratchpad command, for example. This command must be

followed exactly by the data of the three address registers TA1, TA2, and E/S. The master should obtain the

contents of these registers by reading the scratchpad. As soon as the DS28EC20 has received these bytes

correctly, it starts copying the scratchpad data to the requested location, provided that the target memory is not

copy protected, the PF flag is cleared, and there was no Read Memory or Extended Read Memory command

issued between Write Scratchpad and Copy Scratchpad.

DS28EC20: 20Kb 1-Wire EEPROM

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MEMORY FUNCTION COMMANDS

The Memory Function Flowchart (Figure 7) describes the protocols necessary for accessing the memory of the

DS28EC20. The target address registers TA1 and TA2 are used for both read and write. To prevent accidental

changes to the data memory or control registers the device employs a BS-flag indicating a “bad sequence”. The

communication between master and DS28EC20 takes place either at standard speed (default, OD = 0) or at

overdrive speed (OD = 1). If not explicitly set into the Overdrive mode, the DS28EC20 assumes standard speed.

For operation at overdrive speed, the DS28EC20 requires V

PUP

to be 5V ±5%.

WRITE SCRATCHPAD COMMAND [0Fh]

The Write Scratchpad command applies to the data memory and the writable addresses in the register page. After

issuing the Write Scratchpad command, the master must first provide the 2-byte target address, followed by the

data to be written to the scratchpad. The data is written to the scratchpad starting at the byte offset of T[4:0]. The

E/S bits E[4:0] are loaded with the starting byte offset, and increment with each subsequent byte. Effectively, E[4:0]

is the byte offset of the last full byte written to the scratchpad. Only full bytes are accepted. If the last byte is

incomplete its content is ignored and the partial byte flag PF is set. The PF flag is also set if the master ends the

command before a complete target address is transmitted. The PF and BS flags are both cleared when a complete

target address is received.

When executing the Write Scratchpad command, the CRC generator inside the DS28EC20 (Figure 13) calculates a

16-bit CRC of the entire data stream, starting at the command code and ending at the last data byte as sent by the

master. This CRC is generated using the CRC16 polynomial (X

+ X

+ 1) by first clearing the CRC

generator and then shifting in the command code (0Fh) of the Write Scratchpad command, the target addresses

TA1 and TA2 as supplied by the master, and all the data bytes. The master can end the Write Scratchpad

command at any time. However, if the end of the scratchpad is reached (E[4:0] = 11111b), the master can send 16

read-time slots to receive the CRC generated by the DS28EC20.

If a Write Scratchpad is attempted to a write-protected location, the scratchpad is loaded with the data already in

memory, rather than the data transmitted. Similarly, if the target address page is in EPROM mode, the scratchpad

is loaded with the bitwise logical AND of the transmitted data and the data already in memory.

The DS28EC20’s memory address range is 0000h to 0A3Fh. If the bus master sends a target address higher than

this, the DS28EC20’s internal circuitry sets the four most significant address bits to zero as they are shifted into the

internal address register. The Read Scratchpad command reveals the modified target address. The master

identifies such address modifications by comparing the target address read back to the target address transmitted.

If the master does not read the scratchpad, a subsequent Copy Scratchpad command does not work since the

most significant bits of the target address the master sends do not match the value the DS28EC20 expects.

READ SCRATCHPAD COMMAND [AAh]

The Read Scratchpad command allows verifying the target address and the integrity of the scratchpad data. After

issuing the command code, the master begins reading. The first two bytes are the target address. The next byte is

the Ending Offset/Data Status byte (E/S) followed by the scratchpad data beginning at the byte offset (T[4:0]). The

scratchpad data can be different from what the master originally sent. This is of particular importance if the target

address is within the register page or a page in either Write Protection or EPROM modes. See the Write

Scratchpad Command section for details. The master should read through the end of the scratchpad, after which it

receives an inverted CRC16, based on data as it was sent by the DS28EC20. If the master continues reading after

the CRC, all data are logic 1s.

DS28EC20: 20Kb 1-Wire EEPROM

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Figure 7-1. Memory Function Flowchart

0Fh

Write Scratch-

pad ?

Bus Master TX EEPROM

Array Target Address

TA1 (T[7:0]), TA2 (T[15:8])

To Figure 7,

Part

From Figure 7,

Part

Bus Master TX Memory

Function Command

To ROM Functions

Flow Chart (Figure 9)

From ROM Functions

Flow Chart (Figure 9)

Master

TX Reset ?

Master TX Data Byte

To Scratchpad Offset

DS28EC20 sets Scratch

pad Offset = (T[4:0]),

Clears PF, AA, BS

Scrpad. Offset

= 11111b?

DS28EC20 TX CRC16

of Command, Address,

Data Bytes as they were

sent by the bus master

DS28EC20

Increments

Scratchpad

Offset

Master

TX Reset?

Bus Master

RX “1”

Partial

Byte ?

PF = 1

If the memory is write-protected

, the

DS28EC20 copies the data byte from

the target address into the scratchpad.

If the memory is in EPROM mode

, the

DS28EC20 stores the bitwise logical

AND of the transmitted byte and the

data byte from the targeted address

into the scratchpad.

DS28EC20 sets (E[4:0]) =

Scratchpad Offset

Note: The PF Flag is set upon power-

on reset. It is cleared only if a com

plete 16-bit target address is trans

mitted. Sending less than 16 bits for

the target address sets the PF flag.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27

DS28EC20P+

Mfr. #:

Buy DS28EC20P+

Manufacturer:

Maxim Integrated

Description:

EEPROM 20Kb 1-Wire EEPROM

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DS28EC20P+

DS28EC20P+

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