DS28EC20P+ Datasheet DS28EC20P+T, DS28EC20+, DS28EC20+T | P16-P18

DS28EC20: 20Kb 1-Wire EEPROM

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COPY SCRATCHPAD [55h]

The Copy Scratchpad command is used to copy data from the scratchpad to the data memory and the writable

sections of the register page. After issuing the Copy Scratchpad command, the master must provide a 3-byte

authorization pattern, which should have been obtained by an immediately preceding Read Scratchpad command.

This 3-byte pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that

order). If the pattern matches, the target address is valid, the PF and BS flag are not set, and the target memory is

not copy protected, the AA flag is set and the copy begins. The data to be copied is determined by the three

address registers. The scratchpad data from the beginning offset through the ending offset is copied to memory,

starting at the target address. Anywhere from 1 to 32 bytes can be copied with this command. The duration of the

device’s internal data transfer is t

PROG

during which the 1-Wire bus must be idle or actively pulled high. Active

pullup is optional for this device. A pattern of alternating 0s and 1s are transmitted after the data has been copied

until the master issues a reset pulse. If the PF flag or BS flag is set or the target memory is copy protected, the

copy does not begin and the AA flag is not set. The BS flag ensures that Copy Scratchpad is not executed

(blocked) if there was a Read Memory or Extended Read Memory between Write Scratchpad and Copy

Scratchpad.

READ MEMORY [F0h]

The Read Memory command is the general function to read from the DS28EC20. After issuing the command, the

master must provide a 2-byte target address, which should be in the range of 0000h to 0A3Fh. If the target address

is higher than 0A3Fh, the DS28EC20 changes the upper four address bits to 0. After the address is transmitted, the

master reads data starting at the (modified) target address and can continue until address 0A3Fh. If the master

continues reading, the result is FFh. The Read Memory command sequence can be ended at any point by issuing

a reset pulse. Note that this command sets the BS flag. This requires any scratchpad data to be rewritten before it

can be used in a Copy Scratchpad sequence.

EXTENDED READ MEMORY [A5h]

This command works essentially the same way as Read Memory, except for the 16-bit CRC that the DS28EC20

generates and transmits following the last data byte of a memory page. The CRC generated by this command uses

the same polynomial as the Write Scratchpad command. After issuing the command, the master must provide a 2-

byte target address, which should be in the range of 0000h to 0A3Fh. If the target address is higher than 0A3Fh,

the DS28EC20 changes the upper four address bits to 0. After the address is transmitted, the master reads data

starting at the (modified) target address and continuing until the end of a 32-byte page is reached. At that point the

bus master receives an inverted 16-bit CRC. If the master continues reading it receives data starting at the begin-

ning of the next page, followed again by the inverted CRC for that page. Reading beyond the end of the memory is

permissible, but the result is FFh. The Extended Read Memory command sequence can be ended at any point by

issuing a reset pulse. Note that this command sets the BS flag. This requires any scratchpad data to be rewritten

before it can be used in a Copy Scratchpad sequence.

1-Wire BUS SYSTEM

The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS28EC20 is

a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into

three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). The 1-

Wire protocol defines bus transactions in terms of the bus state during specific time slots, which are initiated on the

falling edge of sync pulses from the bus master.

HARDWARE CONFIGURATION

The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at

the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open-drain or tri-state

outputs. The 1-Wire port of the DS28EC20 is open drain with an internal circuit equivalent to that shown in

Figure 8.

A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The DS28EC20 supports both a standard

and overdrive communication speed of 15.4kbps (max) and 90kbps (max), respectively. For operation at overdrive

DS28EC20: 20Kb 1-Wire EEPROM

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speed, the DS28EC20 requires V

PUP

to be 5V ±5%. Note that legacy 1-Wire products support a standard

communication speed of 16.3kbps and overdrive of 142kbps. The slightly reduced rates for the DS28EC20 are a

result of additional recovery times, which in turn were driven by a 1-Wire physical interface enhancement to

improve noise immunity. The value of the pullup resistor primarily depends on the network size and load conditions.

The DS28EC20 requires a pullup resistor of 2.2kΩ (max) at any speed.

The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be

left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16µs

(overdrive speed) or more than 120µs (standard speed), one or more devices on the bus can be reset.

Figure 8. Hardware Configuration

Open-Drain

Port Pin

RX = RECEIVE

TX = TRANSMIT

100Ω

MOSFET

PUP

DATA

PUP

BUS MASTER

DS28EC20 1-Wire PORT

TRANSACTION SEQUENCE

The protocol for accessing the DS28EC20 through the 1-Wire port is as follows:

 Initialization

 ROM Function Command

 Memory Function Command

 Transaction/Data

INITIALIZATION

All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a

reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence

pulse lets the bus master know that the DS28EC20 is on the bus and is ready to operate. For more details, see the

1-Wire Signaling section.

1-Wire ROM FUNCTION COMMANDS

Once the bus master has detected a presence, it can issue one of the seven ROM function commands that the

DS28EC20 supports. All ROM function commands are 8 bits long. See Figure 9 for list of these commands.

READ ROM [33h]

This command allows the bus master to read the DS28EC20’s 8-bit family code, unique 48-bit serial number, and

8-bit CRC. This command can only be used if there is a single slave on the bus. If more than one slave is present

on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-

AND result). The resultant family code and 48-bit serial number result in a mismatch of the CRC.

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MATCH ROM [55h]

The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific

DS28EC20 on a multidrop bus. Only the DS28EC20 that exactly matches the 64-bit ROM sequence responds to

the following memory function command. All other slaves wait for a reset pulse. This command can be used with a

single or multiple devices on the bus.

SEARCH ROM [F0h]

When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or

their registration numbers. By taking advantage of the bus’s wired-AND property, the master can use a process of

elimination to identify the registration numbers of all slave devices. For each bit of the registration number, starting

with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device

participating in the search outputs the true value of its registration number bit. On the second slot, each slave

device participating in the search outputs the complemented value of its registration number bit. On the third slot,

the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the

master stop participating in the search. If both of the read bits are zero, the master knows that slave devices exist

with both states of the bit. By choosing which state to write, the bus master branches in the ROM code tree. After

one complete pass, the bus master knows the registration number of a single device. Additional passes identify the

registration numbers of the remaining devices. Refer to Application Note 187: 1-Wire Search Algorithm

(

www.maxim-ic.com/AN187) for a detailed discussion, including an example.

SKIP ROM [CCh]

This command can save time in a single-drop bus system by allowing the bus master to access the memory

functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a

Read command is issued following the Skip ROM command, data collision occurs on the bus as multiple slaves

transmit simultaneously (open-drain pulldowns produce a wired-AND result).

RESUME [A5h]

To maximize the data throughput in a multidrop environment, the Resume function is available. This function

checks the status of the RC bit and, if it is set, directly transfers control to the memory functions, similar to a Skip

ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM, or

Overdrive Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the

Resume command function. Accessing another device on the bus clears the RC bit, preventing two or more

devices from simultaneously responding to the Resume command function.

OVERDRIVE SKIP ROM [3Ch]*

On a single-drop bus this command can save time by allowing the bus master to access the memory functions

without providing the 64-bit ROM code. Unlike the normal Skip ROM command, the Overdrive Skip ROM sets the

DS28EC20 in the Overdrive mode (OD = 1). All communication following this command must occur at overdrive

speed until a reset pulse of minimum 480µs duration resets all devices on the bus to standard speed (OD = 0).

When issued on a multidrop bus, this command sets all overdrive-supporting devices into Overdrive mode. To

subsequently address a specific overdrive-supporting device, a reset pulse at overdrive speed must be issued

followed by a Match ROM or Search ROM command sequence. This speeds up the time for the search process. If

more than one slave supporting overdrive is present on the bus and the Overdrive Skip ROM command is followed

by a Read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain

pulldowns produce a wired-AND result).

OVERDRIVE MATCH ROM [69h]*

The Overdrive Match ROM command followed by a 64-bit ROM sequence transmitted at overdrive speed allows

the bus master to address a specific DS28EC20 on a multidrop bus and to simultaneously set it in Overdrive mode.

Only the DS28EC20 that exactly matches the 64-bit ROM sequence responds to the subsequent memory function

command. Slaves already in Overdrive mode from a previous Overdrive Skip or successful Overdrive Match

command remain in Overdrive mode. All overdrive-capable slaves return to standard speed at the next Reset Pulse

of minimum 480µs duration. The Overdrive Match ROM command can be used with a single or multiple devices on

the bus.

* For operation at overdrive speed, the DS28EC20 requires V

PUP

to be 5V ±5%.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27

DS28EC20P+

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EEPROM 20Kb 1-Wire EEPROM

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DS28EC20P+

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