24
LTC1735-1
Design Example
As a design example, assume V
IN
= 12V (nominal), V
IN
=
22V (max), V
OUT
= 1.5V, I
MAX
= 12A and f = 300kHz,
R
SENSE
and C
OSC
can immediately be calculated:
R
SENSE
= 50mV/12A = 0.042Ω
C
OSC
= 1.61(10
7
)/(300kHz) – 11pF = 43pF
Assume a 1.2µH inductor and check the actual value of the
ripple current. The following equation is used :
∆I
V
fL
V
V
L
OUT OUT
IN
=
()()
–1
The highest value of the ripple current occurs at the
maximum input and output voltages:
∆I
V
kHz H
V
V
A
L
=
µ
=
15
300 1 2
1
15
22
39
.
(. )
–
.
.
The maximum ripple current is 32% of maximum output
current, which is about right.
Next, verify the minimum on-time of 200ns is not violated.
The minimum on-time occurs at maximum V
IN
and mini-
mum V
OUT
.
t
V
Vf
V
V kHz
ns
ON MIN
OUT
IN MAX
()
()
.
()
== =
15
22 300
227
The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Fairchild FDS6612A results
in; R
DS(ON)
= 0.03Ω, C
RSS
= 80pF. At maximum input
voltage with T(estimated) = 50°C:
P
V
V
CC
V A pF kHz
mW
MAIN
=
()
+°°
[]
Ω
()
+
()()( )( )
=
15
22
12 1 0 005 50 25 0 03
1 7 22 12 80 300
568
2
2
.
( . )( – ) .
.
Because the duty cycle of the bottom MOSFET is much
greater than the top, two larger MOSFETs must be paral-
leled. Choosing Fairchild FDS6680A MOSFETs yields a
parallel R
DS(ON)
of 0.0065Ω. The total power dissipation
for both bottom MOSFETs, again assuming T = 50°C, is:
P
VV
V
A
mW
SYNC
=
()()
Ω
()
=
22 1 5
22
12 1 1 0 0065
959
2
–.
..
Thanks to current foldback, the bottom MOSFET dissipa-
tion in short circuit will be less than under full-load
conditions.
C
IN
is chosen for an RMS current rating of at least 6A at
temperature. C
OUT
is chosen with an ESR of 0.01Ω for low
output ripple. The output ripple in continuous mode will be
highest at the maximum input voltage. The output voltage
ripple due to ESR is approximately:
V
ORIPPLE
= R
ESR
(∆I
L
) = 0.01Ω(3.9A) = 39mV
P-P
Since the output voltage is below 2.4V, the output resistive
divider will need to be sized to not only set the output
voltage but also to absorb the SENSE pins specified input
current.
R MAX k
V
VV
k124
08
24 15
21 3()
.
.–.
.=
=
Choosing 1% resistors: R1 = 21k and R2 = 18.7k yields an
output voltage of 1.512V.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1735-1. These items are also illustrated graphically in
the layout diagram of Figure 12. Check the following in
your layout:
1. Are the signal and power grounds segregated? The
LTC1735-1 PGND pin should tie to the ground plane
close to the input capacitor(s). The SGND pin should
then connect to PGND and all components that connect
to SGND should make a single-point tie to the SGND
pin. The synchronous MOSFET source should connect
to the input capacitor(s) ground.
2.
Does the V
OSENSE
pin connect directly to the feedback
resistors? The resistive divider R1, R2 must be con-
nected between the (+) plate of C
OUT
and signal ground.
The 47pF capacitor from V
OSENSE
to SGND should be
as close as possible to the LTC1735-1. Be careful
locating the feedback resistors too far away from the
APPLICATIO S I FOR ATIO
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