7
LTC1735-1
C
OSC
(Pin 1): External capacitor C
OSC
from this pin to
ground sets the operating frequency.
RUN/SS (Pin 2): Combination of Soft-Start and Run
Control Inputs. A capacitor to ground at this pin sets the
ramp time to full current output. The time is approximately
1.25s/µF. Forcing this pin below 1.5V causes the device to
be shut down. In shutdown all functions are disabled.
Latchoff overcurrent protection is also invoked via this pin
as described in the Applications Information section.
I
TH
(Pin 3): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 2.4V.
PGOOD (Pin 4): Open-Drain Logic Output and Forced
Continuous/Synchronization Input. The PGOOD pin is
pulled to ground when the voltage on the V
OSENSE
pin is
not within ±7.5% of its nominal set point. If power good
indication is not needed, this pin can be tied to ground to
force continuous synchronous operation. Clocking this
pin with a signal above 1.5V
P-P
synchronizes the internal
oscillator to the external clock. Synchronization only
occurs while the main output is in regulation (PGOOD not
internally pulled low). When synchronized, Burst Mode
operation is disabled but cycle skipping is allowed at low
load currents. This pin requires a pull-up resistor for
power good indication. Do not connect this pin directly to
an external source (or INTV
CC
). Do not exceed INTV
CC
on
this pin.
SENSE
(Pin 5): The (–) Input to the Current Comparator.
SENSE
+
(Pin 6): The (+) Input to the Current Comparator.
Built-in offsets between SENSE
+
and SENSE
pins in
conjunction with R
SENSE
set the inductor current trip
threshold.
V
OSENSE
(Pin 7): Receives the feedback voltage from an
external resistive divider across the output.
SGND (Pin 8): Small-Signal Ground. All small-signal
components such as C
OSC
, C
SS
, the feedback divider plus
the loop compensation resistors and capacitor(s) should
single-point tie to this pin. This pin should, in turn, connect
to PGND.
EXTV
CC
(Pin 9): Input to the Internal Switch Connected to
INTV
CC
. This switch closes and supplies V
CC
power when-
ever EXTV
CC
is higher than 4.7V. See EXTV
CC
connection
in Applications Information section. Do not exceed 7V on
this pin and ensure EXTV
CC
is V
IN
.
PGND (Pin 10): Driver Power Ground. This pin connects
to the source of the bottom N-channel MOSFET, the anode
of the Schottky diode and the (–) terminal of C
IN
.
BG (Pin 11): High Current Gate Drive for the Bottom
N-Channel MOSFET. Voltage swing at this pin is from
ground to INTV
CC
.
INTV
CC
(Pin 12): Output of the Internal 5.2V Low Dropout
Regulator and EXTV
CC
Switch. The driver and control
circuits are powered from this voltage. Decouple to power
ground with a 1µF ceramic capacitor placed directly adja-
cent to the IC together with a minimum of 4.7µF tantalum
or other low ESR capacitor.
V
IN
(Pin 13): Main Supply Pin. This pin must be closely
decoupled to power ground.
SW (Pin 14): Switch Node Connection to Inductor and
Bootstrap Capacitor. Voltage swing at this pin is from a
Schottky diode (external) voltage drop below ground to
V
IN
.
BOOST (Pin 15): Supply to Topside Floating Driver. The
bootstrap capacitor is returned to this pin. Voltage swing
at this pin is from a diode drop below INTV
CC
to V
IN
+
INTV
CC
.
TG (Pin 16): High Current Gate Drive for Top N-Channel
MOSFET. This is the output of a floating driver with a
voltage swing equal to INTV
CC
superimposed on the
switch node voltage SW.
PI FU CTIO S
UUU
8
LTC1735-1
OPERATIO
U
(Refer to Functional Diagram)
FU CTIO AL DIAGRA
UU
W
SW
+
+
0.86V
+
0.55V
2.4V
0.8V
0.86V
I
1
+
I
2
+
EA
A
BURST
DISABLE
FC
OV
g
m
=1.3m
B
+
4.8V
IREV
+
+
F
FC
INTV
CC
S
R
Q
DROP
OUT
DET
0.8V
REF
SWITCH
LOGIC
SD
6V
R1
RUN/SS
C
SS
R
C
V
OSENSE
V
FB
1.2µA
RUN
SOFT-
START
+
OVER-
CURRENT
LATCHOFF
SD
I
TH
C
C
0.17µA
OSC
4(V
FB
)
BUFFERED
I
TH
SLOPE COMP
+ +
3mV
ICMP
R2
2k
45k
BOT
TOP ON
FORCE BOT
45k
100k
INTV
CC
30k 30k
SENSE
+
SENSE
SYNC
1.2V
+
0.74V
0.8V
C
TOP
UVL
BOT
INTV
CC
5.2V
LDO
REG
V
IN
+
C
INTVCC
+
INTV
CC
BG
PGND
V
IN
V
IN
BOOST
TG
INTV
CC
C
B
D
B
D
1
L
V
OUT
R
SENSE
C
OUT
C
OSC
+
C
IN
EXTV
CC
SGNDC
OSC
1735-1 FD
1
PGOOD
4 8
13
15
16
14
12
11
10
9563
2
7
Main Control Loop:
The LTC1735-1 uses a constant frequency, current mode
step-down architecture. During normal operation, the top
MOSFET is turned on each cycle when the oscillator sets
the RS latch, and turned off when the main current
comparator I
1
resets the RS latch. The peak inductor
current at which I
1
resets the RS latch is controlled by the
voltage on Pin I
TH
, which is the output of error amplifier
EA. Pin V
OSENSE
, described in the Pin Functions, allows EA
to receive an output feedback voltage V
FB
from the external
resistive divider. When the load current increases, it
causes a slight decrease in V
FB
relative to the 0.8V refer-
ence, which in turn causes the I
TH
voltage to increase until
the average inductor current matches the new load cur-
rent. While the top MOSFET is off, the bottom MOSFET is
turned on until either the inductor current starts to reverse,
as indicated by current comparator I
2
, or the beginning of
the next cycle.
The top MOSFET driver is powered from a floating boot-
strap capacitor C
B
. This capacitor is normally recharged
from INTV
CC
through an external Schottky diode when the
top MOSFET is turned off. As V
IN
decreases towards V
OUT
,
the converter will attempt to turn on the top MOSFET con-
tinuously (“dropout’’). A dropout counter detects this con-
dition and forces the top MOSFET to turn off for about 500ns
every tenth cycle to recharge the bootstrap capacitor.
9
LTC1735-1
OPERATIO
U
(Refer to Functional Diagram)
The main control loop is shut down by pulling Pin 2 (RUN/
SS) low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor C
SS
. When
C
SS
reaches 1.5V, the main control loop is enabled with the
I
TH
voltage clamped at approximately 30% of its maximum
value. As C
SS
continues to charge, I
TH
is gradually re-
leased allowing normal operation to resume. If V
OUT
has
not reached 70% of its final value when C
SS
has charged
to 4.1V, latchoff can be invoked as described in the
Applications Information section.
The internal oscillator can be synchronized to an external
clock applied though a series resistor to the PGOOD pin
and can lock to a frequency between 90% and 130% of its
nominal rate set by capacitor C
OSC
.
An overvoltage comparator OV guards against transient
overshoots (>7.5%) as well as other more serious
conditions that may overvoltage the output. In this case,
the top MOSFET is turned off and the bottom MOSFET is
turned on until the overvoltage condition is cleared.
Foldback current limiting for an output shorted to ground
is provided by amplifier A. As V
OSENSE
drops below 0.6V,
the buffered I
TH
input to the current comparator is gradually
pulled down to a 0.86V clamp. This reduces peak inductor
current to about 1/4 of its maximum value.
Low Current Operation
The LTC1735-1 has three low current modes controlled
by the PGOOD pin. Burst Mode operation is selected when
the PGOOD pin is above 0.8V (typically tied through a
resistor to INTV
CC
). During Burst Mode operation, if the
error amplifier drives the I
TH
voltage below 0.86V, the
buffered I
TH
input to the current comparator will be
clamped at 0.86V. The inductor current peak is then held
at approximately 20mV/R
SENSE
(about 1/4 of maximum
output current). If I
TH
then drops below 0.5V, the Burst
Mode comparator B will turn off both MOSFETs to maxi-
mize efficiency. The load current will be supplied solely by
the output capacitor until I
TH
rises above the 60mV
hysteresis of the comparator and switching is resumed.
Burst Mode operation is disabled by comparator F when
the PGOOD pin is brought below 0.8V. This forces
continuous operation and assists in controlling voltage
regulation. If the output voltage is not within 7.5% of its
nominal value the PGOOD open-drain output will be
pulled low and Burst Mode operation will be disabled.
Foldback Current, Short-Circuit Detection
and Short-Circuit Latchoff
The RUN/SS capacitor, C
SS
, is used initially to limit the
inrush current of the switching regulator. After the con-
troller has been started and been given adequate time to
charge up the output capacitors and provide full load
current, C
SS
is used as a short-circuit time-out circuit. If
the output voltage falls to less than 70% of its nominal
output voltage, C
SS
begins discharging on the assumption
that the output is in an overcurrent and/or short-circuit
condition. If the condition lasts for a long enough period
as determined by the size of the C
SS
, the controller will be
shut down until the RUN/SS pin voltage is recycled. This
built-in latchoff can be overridden by providing a current
>5µA at a compliance of 5V to the RUN/SS pin. This
current shortens the soft-start period but also prevents net
discharge of C
SS
during an overcurrent and/or short-
circuit condition. Foldback current limiting is activated
when the output voltage falls below 70% of its nominal
level whether or not the short-circuit latchoff circuit is
enabled.
INTV
CC
/EXTV
CC
Power
Power for the top and bottom MOSFET drivers and most
of the internal circuitry of the LTC1735-1 is derived from
the INTV
CC
pin. When the EXTV
CC
pin is left open, an
internal 5.2V low dropout regulator supplies the INTV
CC
power from V
IN
. If EXTV
CC
is raised above 4.7V, the
internal regulator is turned off and an internal switch
connects EXTV
CC
to INTV
CC
. This allows a high efficiency
source, such as the primary or a secondary output of the
converter itself, to provide the INTV
CC
power. Voltages up
to 7V can be applied to EXTV
CC
for additional gate drive
capability.
To provide clean start-up and to protect the MOSFETs,
undervoltage lockout is used to keep both MOSFETs off
until the input voltage is above 3.5V.

LTC1735CGN-1#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Hi Eff Sync Buck Sw Reg
Lifecycle:
New from this manufacturer.
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