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73S8023C-IM/F

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73S8023C Data Sheet DS_8023C_019
10 Rev. 1.5
6 Power Down
A power down function is provided via the PWRDN pin (active high). When activated, the Power Down
(PD) mode disables all the internal analog functions, including the card analog interface, the oscillators
and the DC-DC converter, to put the 73S8023C in its lowest power consumption mode. PD mode is only
allowed in the deactivated condition (out of a card session, when the CMDVCC signal is driven high from
the host controller).
The host controller invokes the power down state when it is desirable to save power. The signals PRES
and PRES remain functional in PD mode such that a card insertion sets OFF high. The micro-controller
must then set PWRDN low and wait for the internal stabilization time prior to starting any card session
(prior to turning CMDVCC low).
Resumption of the normal mode occurs approximately 10 ms (stabilization of the internal oscillators and
reset of the circuitry) after PWRDN is set low. No card activation should be invoked during this 10 ms
time period. If a card is present, OFF can be used as an indication that the circuit has completed its
recovery from power-down state. OFF will go high at the end of the stabilization period. Should
CMDVCC go low during PWRDN = 1, or within the 10 ms internal stabilization / reset time, it will not be
taken into account and the card interface will remain inactive. Since CMDVCC is taken into account on
its edges, it should be toggled high and low again after the 10 ms to activate a card.
Figure 2 illustrates the sequencing of the PD and Normal modes. PWRDN must be connected to GND if
the power down function is not used.
Figure 2: Power Down Mode Operation: CS = high
7 Over-temperature Monitor
A built-in detector monitors die temperature. When an over-temperature condition occurs, a card
deactivation sequence is initiated, and an error or fault condition is reported to the system controller.
PRES
OFF
PWRDN
Internal RC OSC
CMDVCC
OFF follows PRES regardless of PWRDN
PWRDN during a card
session has no effect
After setting PWRDN = 0,
the controller must wait at
least 10ms before setting
CMDVCC=0
EMV / ISO deactivation
time ~= 100 uS
~10ms
PWRDN has effect when
the cardi s deactivated
DS_8023C_019 73S8023C Data Sheet
Rev. 1.5 11
8 Activation and Deactivation
8.1 Activation Sequence (Synchronous Mode)
The 73S8023C smart card interface IC has an internal ~10 ms delay at power-on reset or on application
of V
DD
> V
DDF
1. CMDVCC is set low.
. No activation is allowed at this time. CMDVCC (edge triggered) must then be set low to
activate the card.
The following steps list the activation sequence and the timing of the card control signals when the
system controller sets CMDVCC low:
2. Turn on V
CC
and I/O (AUX1, AUX2) to reception mode at the end of (t
ACT
3. RST is a copy of RSTIN and CLK is a copy of STROBE after (t
).
1
).
Figure 3: Activation Sequence – Synchronous Mode
8.2 Deactivation Sequence (Synchronous Mode)
Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in
the event of hardware faults. Hardware faults are over-current, overheating, V
DD
1. RST goes low at time t
fault and card extraction
during the session and are indicated to the system controller by the fall of OFF.
The following steps list the deactivation sequence and the timing of the card control signals when the
system controller sets the CMDVCC high or a fault condition sets OFF low:
1
2. CLK stops low at time t
.
2
3. I/O goes low at time t
.
3
4. V
. Out of reception mode.
CC
is shut down at time t
4
. After a delay t
5
(discharge of the V
CC
capacitor), V
CC
is low.
CMDVCC
VCC
IO
CLK
RSTIN
t
ACT
t
1
RST
STROBE
t
ACT
~= 500µs
t
1
> 0.5
µ
s after t
ACT
, RST = RSTIN, CLK = STROBE
73S8023C Data Sheet DS_8023C_019
12 Rev. 1.5
CMDVCC
VCC
IO
OFF
RSTIN
RST
STROBE
CLK
t
0
- Deactivation starts after CMDVCC is set high or OFF falls due to card removal or fault
t
4
- VCC is shut down
(Note: Host should set STROBE low when CMDVCC is set high, otherwise CLK may be truncated.
CLK truncation may occur if an OFF event is triggered)
t
3
- IO falls approx 2us after CLK falls
t
1
- RST falls approx. 0.5us after deactivation begins
t
2
- CLK falls approx. 7.5us after RST falls
-- OR --
t
0
t
1
t
2
t
3
t
5
t
4
t
5
- VCC goes to 0 after discharge of VCC capacitor, approx 100us after deactivation begins
Figure 4: Synchronous Deactivation Operation – CKSEL = High
8.3 Activation Sequence (Asynchronous Mode)
The 73S8023C smart card interface IC has an internal 10 ms delay at power-on reset or upon application
of V
DD
> V
DDF
1. CMDVCC is set low.
or upon exit of Power Down mode. The card interface may only be activated when OFF is
high which indicates a card is present. No activation is allowed at this time. CMDVCC (edge triggered)
must then be set low to activate the card.
The following steps list the activation sequence and the timing of the card control signals when the
system controller sets CMDVCC low while the RSTIN is low:
2. Next, the internal V
CC
control circuit checks the presence of V
CC
at the end of t
1
. In normal operation,
the voltage V
CC
to the card becomes valid during t
1
. If V
CC
does not become valid, then OFF goes
low to report a fault to the system controller, and the power V
CC
3. Turn I/O (AUX1, AUX2) to reception mode at the end of t
to the card is turned off.
2
4. CLK is applied to the card at the end of t
.
3
5. RST is a copy of RSTIN after t
.
4
. RSTIN may be set high before t
4
, however the sequencer won’t set
RST high until 42000 clock cycles after the start of CLK.
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73S8023C-IM/F

Mfr. #:
Buy 73S8023C-IM/F
Manufacturer:
Maxim Integrated
Description:
I/O Controller Interface IC Smart Card Interface ISO7816-3 & EVM4.0
Lifecycle:
New from this manufacturer.
Delivery:
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