73S8023C-IM/F Datasheet 73S8023C-IM/F, 73S8023C-IMR/F | P4-P6

73S8023C Data Sheet DS_8023C_019

4 Rev. 1.5

Figures

Figure 1: 73S8023C Block Diagram ............................................................................................................. 2

Figure 2: Power Down Mode Operation: CS = high

.................................................................................... 10

Figure 3: Activation Sequence – Synchronous Mode

................................................................................. 11

Figure 4: Synchronous Deactivation Operation – CKSEL = High

............................................................... 12

Figure 5: Asynchronous Activation Sequence – RSTIN Low When CMDVCC Goes Low

......................... 13

Figure 6: Asynchronous Activation Sequence – Timing Diagram #2

......................................................... 13

Figure 7: Asynchronous Deactivation Sequence

........................................................................................ 14

Figure 8: Timing Diagram – Management of the Interrupt Line OFF

.......................................................... 15

Figure 9: I/O and I/OUC State Diagram

...................................................................................................... 16

Figure 10: I/O – I/OUC Delays Timing Diagram

.......................................................................................... 16

Figure 11: 73S8023C – Typical Application Schematic

.............................................................................. 17

Figure 12: DC – DC Converter efficiency (V

= 5 V) ................................................................................ 20

Figure 13: DC – DC Converter Efficiency (V

= 3 V) ................................................................................ 20

Figure 14: 32-QFN Mechanical Drawing

..................................................................................................... 24

Figure 15: 32-QFN 73S8023C Pin Out

....................................................................................................... 25

Table

Table 1: Choice of VCC Pin Capacitor .......................................................................................................... 8

DS_8023C_019 73S8023C Data Sheet

Rev. 1.5 5

1 Pin Description

1.1 Card Interface

Name Pin Description

I/O 9 Card I/O: Data signal to/from card. Includes a pull-up resistor to V

CC.

AUX1 11 AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to V

CC.

AUX2 10 AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to V

CC.

RST 14 Card reset: Provides reset (RST) signal to card.

CLK 13

Card clock: Provides clock (CLK) signal to card. The rate of this clock is

determined by crystal oscillator frequency and CLKDIV selections.

PRES 7

Card Presence switch: Active high indicates card is present. Includes a

pull-down current source.

PRES

Card Presence switch: Active low indicates card is present. Includes a pull-up

current source.

VCC 15

Card power supply: Logically controlled by sequencer, output of DC-DC

converter. Requires an external filter capacitor to the card GND.

GND 12 Card ground.

1.2 Miscellaneous Inputs and Outputs

Name Pin Description

XTALIN 23

Crystal oscillator input: can either be connected to crystal or driven as a

source for the card clock.

XTALOUT 24

Crystal oscillator output: connected to crystal. Left open if XTALIN is being

used as external clock input.

VDDF_ADJ 17

fault threshold adjustment input: this pin can be used to adjust V

DDF

value (that controls deactivation of the card). Must be left open if unused.

NC 4 Non-connected pin. Must be left open.

1.3 Power Supply and Ground

Name Pin Description

VDD 3, 20

System controller interface supply voltage: Supply voltage for internal power

supply and DC-DC converter power supply source.

GND 1 DC-DC converter ground.

GND 21 Digital ground.

LIN 2

External inductor. Connect external inductor from pin 2 to V

. Keep the

inductor close to pin 2.

73S8023C Data Sheet DS_8023C_019

6 Rev. 1.5

1.4 Microcontroller Interface

Name Pin Description

CMDVCC 18

Command V

(negative assertion): Logic low on this pin causes the DC-DC

converter to ramp the V

supply to the card and initiates a card activation

sequence.

5V/#V

5 volt / 3 volt card selection: Logic one selects 5 volts for V

and card

interface, logic low selects 3 volt operation. When the part is to be used with

a single card voltage, this pin should be tied to either GND or V

. However,

it includes a high impedance pull-up resistor to default this pin high (selection

of 5V card) when unconnected

PWRDN 5

Power Down control input: Active High. When Power Down (PD) mode is

activated, all internal analog functions are disabled to place the 73S8023C in

its lowest power consumption mode. The PD mode is allowed only out of a

card session (PWRDN high is ignored when CMDVCC = 0). Must be tied to

ground when power down function is not used.

CLKDIV1

CLKDIV2

Sets the divide ratio from the XTALIN oscillator (or external clock input) to the

card clock. These pins include pull-down resistors.

CLKDIV1 CLKDIV2 Clock Rate

XTALIN/8

XTALIN/4

XTALIN/2

XTALIN

OFF 22

Interrupt signal to the processor: Active Low. Multi-function indicating fault

conditions and card presence. Open drain output configuration; it includes an

internal 20 kΩ pull-up to V

DD.

RSTIN 19 Reset Input: This signal controls the RST signal to the card.

I/OUC 26

System controller data I/O to/from the card. Includes internal pull-up resistor

to V

DD.

AUX1UC 27

System controller auxiliary data I/O to/from the card. Includes internal pull-up

resistor to V

DD.

AUX2UC 28

System controller auxiliary data I/O to/from the card. Includes internal pull-up

resistor to V

DD.

CS 8

When CS = 1, the control and signal pins are configured normally. When CS

is set low, signals CMDVCC, RSTIN, PWRDN, 5V/#V, CLKDIV1, CLKDIV2,

CLKSEL are latched. I/OUC, AUX1UC, and AUX2UC are set to high

impedance pull-up mode and won’t pass data to or from the smart card. OFF

output is tri-stated.

CLKSEL 16

Selects CLK and RST operational mode. When CLKSEL is low (default), the

circuit is configured for asynchronous card operation and the sequencer

manages the control of CLK and RST. When CLKSEL is high, the signal

CLK is a buffered copy of STROBE and the signal RST is directly controlled

by RSTIN.

STROBE 25 When CLKSEL = 1, the signal CLK is controlled directly by STROBE.

CLKOUT 32 CLKOUT is the buffered version of the signal on pin XTALIN.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27

73S8023C-IM/F

Mfr. #:

Buy 73S8023C-IM/F

Manufacturer:

Maxim Integrated

Description:

I/O Controller Interface IC Smart Card Interface ISO7816-3 & EVM4.0

Lifecycle:

New from this manufacturer.

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73S8023C-IM/F

73S8023C-IM/F

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