73S8023C-IM/F Datasheet 73S8023C-IM/F, 73S8023C-IMR/F | P7-P9

DS_8023C_019 73S8023C Data Sheet

Rev. 1.5 7

2 System Controller Interface

• The CS (chip select) input allows multiple devices to operate in parallel. When CS is high, the system

interface signals operate as described. When CS is taken low, the system interface signals are

latched internally. The pins I/OUC, AUX1UC, and AUX2UC are weakly pulled up and the OFF signal

is put into a high impedance state.

• The CLKSEL signal selects between synchronous and asynchronous operation. When CLKSEL is

low, asynchronous operation is selected. When CLKSEL is high, synchronous operation is selected.

• Digital inputs allow direct control of the card interface from the host as follows:

 Pin CMDVCC: When set low, starts an activation sequence if a card is present.

 Pin 5V/#V: Defines the card voltage.

• The card I/O and Reset signals have their corresponding controller I/Os to be connected directly to

the host:

 Pin RSTIN: controls the card RST signal. When enabled by the sequencer, RST is equal to

RSTIN for both synchronous and asynchronous modes.

 Pin I/OUC: data transfer to card I/O contact.

 Pins AUX1UC and AUX2UC (auxiliary I/O lines associated to the auxiliary I/Os which are

connected to the C4 and C8 card connector contacts).

• Two digital inputs control the card clock frequency division rate: CLKDIV1 and CLKDIV2 define the

card clock frequency from the input clock frequency (crystal or external clock). The division rate is

defined as follows:

CLKDIV2 CLKDIV1 CLK

0 0

⅛ XTAL

0 1 XTAL

1 0 ¼ XTAL

1 1 ½ XTAL

When the division rate is equal to 1 (CLKDIV2 =0 and CLKDIV1 = 1), the duty-cycle of the

card clock depends on the duty-cycle and waveform of the signal applied on the pin XTALIN.

When other division rates are used, the 73S8023C circuitry guarantees a duty-cycle in the

range 45% to 55%, conforming to ISO-7816-3 and EMV 4.1 specifications.

• Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about

the card presence only (low = no card in the reader). When CMDVCC is set low (Card activation

sequence requested from the host), a low level on OFF means a fault has been detected (e.g. card

removedl during a card session, or voltage fault, or thermal / over-current fault) that automatically

initiates a deactivation sequence.

• Power Down: The PWRDN pin is a digital input that allows the host controller to put the 73S8023C in

its Power Down state. This pin can only be activated outside of a card session.

• The CLKOUT signal is a buffered output of the signal applied to the XTALIN pin whether it is an

external clock source or it is configured as a crystal oscillator. CLKOUT can be used when using

multiple 73S8023C devices to share a single clock signal.

• The STROBE input directly drives the smart card CLK signal when operating in synchronous mode.

STROBE is ignored in asynchronous mode.

73S8023C Data Sheet DS_8023C_019

8 Rev. 1.5

3 Oscillator

The 73S8023C device has an on-chip oscillator that can generate the smart card clock using an external

crystal (connected between the pins XTALIN and XTALOUT) to set the oscillator frequency. When the

card clock signal is available from another source, it can be connected to the pin XTALIN, and the pin

XTALOUT should be left unconnected. Signal CLKOUT is the buffered version of the signal on XTALIN.

4 DC-DC Converter – Card Power Supply

An internal DC-DC converter provides the card power supply. This converter is able to provide either 3 V

or 5 V card voltage from the power supply applied on the V

pin. The digital ISO-7816-3 sequencer

controls the converter. Card voltage selection is carried out by the digital input 5V/#V.

The circuit is an inductive step-up converter/regulator. The external components required are 2 filter

capacitors on the power-supply input V

(next to the LIN pin, 100 nF + 10 µF), an inductor, and an

output filter capacitor on the card power supply V

. The circuit performs regulation by activating the

step-up operation when V

is below a set point of 5.0 or 3.0 volts minus a comparator hysteresis voltage

and the input supply V

is less than the set point for V

. When V

is greater than the set point for V

= 3.6 V, V

=3 V) the circuit operates as a linear regulator.

Depending on the inductor values, the voltage converter can provide current on V

as high as 100 mA.

The circuit provides over-current protection and limits I

to 150 mA. When an over-current condition is

sensed, the circuit initiates a deactivation sequence from the control logic and reports back to the host

controller a fault on the interrupt output OFF.

Choice of the inductor

The nominal inductor value is 10 µH, rated for 400 mA. The inductor is connected between LIN (pin 2)

and the V

supply voltage. The inductor value can be optimized to meet a particular configuration

CC_MAX

). The inductor should be located on the PCB as close as possible to the LIN pin of the IC.

Choice of the V

Depending on the applications, the requirements in terms of both the V

capacitor

Table 1

minimum voltage and the

transient currents that the interface must provide to the card are different. shows the

recommended capacitors for each V

Table 1: Choice of VCC Pin Capacitor

power supply configuration and applicable specification.

Specification Requirement Application

Specification

Min V

Max Transient

Current Charge

Voltage

Allowed During

Transient Current

Capacitor

Type

Capacitor

Value

EMV 4.1 4.6 V 30 nAs

X5R/X7R w/

ESR < 100 mΩ

3.3 µF

ISO-7816-3 4.5 V 20 nAs

1 µF

NDS 4.65 V 40 nAs

3.3 µF

DS_8023C_019 73S8023C Data Sheet

Rev. 1.5 9

5 Voltage Supervision

Two voltage supervisors constantly check the presence of the voltages V

and V

. A card deactivation

sequence is triggered upon a fault detected by these voltage supervisors.

The digital circuitry is powered by the power supply applied on the VDD pin. V

also defines the voltage

range for the interface with the system controller. The V

Voltage supervisor is also used to initialize the

ISO-7816-3 sequencer at power-on, and also to deactivate the card at power-off or upon a fault. The

voltage threshold of the V

voltage supervisor is internally set by default to 2.3 V nominal. However, it

may be desirable, in some applications, to modify this threshold value. The pin VDDF_ADJ (pin 17) is

used to connect an external resistor R

EXT

to ground to raise the V

fault voltage to another value, V

DDF

The resistor value is defined as follows:

EXT

= 180 kΩ /(V

DDF

An alternative (more accurate) method of adjusting the V

- 2.33)

Figure 11: 73S8023C – Typical Application

Schematic

fault voltage is to use a resistive network of

R3 from the pin to supply and R1 from the pin to ground (see

). In order to set the new threshold voltage, the equivalent resistance must be determined.

This resistance value will be designated Kx. Kx is defined as R1/(R1+R3). Kx is calculated as:

Kx = (2.649 / V

) - 0.6042 where V

is the desired new threshold voltage.

To determine the values of R1 and R3, use the following formulas:

R3 = 72000 / Kx R1 = R3*(Kx / (1 – Kx))

Taking the example above, where a V

fault threshold voltage of 2.7 V is desired, solving for Kx gives:

 Kx = (2.649 / 2.7) - 0.6042 = 0.377

Solving for R3 gives:  R3 = 72000 / 0.377 = 191 kΩ.

Solving for R1 gives:  R1 = 191000 *(0.377 / (1 – 0.377)) = 115.6 kΩ.

Using standard 1 % resistor values gives R3 = 191 kΩ and R1 = 115 kΩ. These values give an

equivalent resistance of Kx = 0.376, a 0.3% error.

Using 1% external resistors and a parallel resistance of 72 k ohms will result in a +/- 6% tolerance in the

value of VDD Fault. The sources of variation due to integrated circuit process variations and mismatches

include the internal reference voltage (less than +/- 1%), the internal comparator hysteresis and offset

(less than +/- 1.7% for part-to-part, processing and environment), the internal resistor value mismatch and

value variations (less than 1.8%), and the external resistor values (1%).

If the 2.3 V default threshold is acceptable, this pin must be left unconnected.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27

73S8023C-IM/F

Mfr. #:

Buy 73S8023C-IM/F

Manufacturer:

Maxim Integrated

Description:

I/O Controller Interface IC Smart Card Interface ISO7816-3 & EVM4.0

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73S8023C-IM/F

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