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MT72HTS1G72PY-53EE1

P1-P3P4-P6P7-P9P10-P12P13-P15
PDF: 09005aef82d283a8/Source: 09005aef82d28271 Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTS72C1Gx72.fm - Rev. A 8/07 EN
10 ©2007 Micron Technology, Inc. All rights reserved.
8GB (x72, ECC, QR) 240-Pin DDR2 SDRAM RDIMM
Register and PLL Specifications
Notes: 1. PLL timing and switching specifications are critical for proper operation of the DDR2 DIMM.
This is a subset of parameters for the specific PLL used. Detailed PLL information is available
in JEDEC standard JESD82-08.1.
Table 10: PLL Specifications
CU877 device or equivalent JESD82-8.01
Parameter Symbol Pins Condition Min Max Units
DC high-level input
voltage
V
IH RESET# LVCMOS 0.65 × VDD –V
DC low-level input
voltage
V
IL RESET# LVCMOS – 0.35 × VDD V
Input voltage (limits)
V
IN RESET#, CK,
CK#
––0.3VDDQ + 0.3 V
DC high-level input
voltage
V
IH CK, CK# Differential input 0.65 × VDD –V
DC low-level input
voltage
V
IL CK, CK# Differential input – 0.35 × VDD V
Input differential-pair
cross voltage
V
IX CK, CK# Differential input (VDDQ/2) - 0.15 (VDDQ/2) + 0.15 V
Input differential
voltage
V
ID(DC) CK, CK# Differential input 0.3 VDDQ + 0.4 V
Input differential
voltage
V
ID(AC) CK, CK# Differential input 0.6 VDDQ + 0.4 V
Input current
I
I RESET# VI = VDDQ or VSSQ–10 10µA
CK, CK# VI = VDDQ or VSSQ –250 250 µA
Output disabled
current
I
ODL – RESET# = VSSQ; VI =VIH(AC)
or VIL(DC)
100 – µA
Static supply current
I
DDLD – CK = CK# = LOW – 500 µA
Dynamic supply
I
DD n/a CK, CK# = 270 MHz, all
outputs open
(not connected to PCB)
–300mA
Input capacitance
C
IN Each input VI = VDDQ or VSSQ2 3pF
Table 11: PLL Clock Driver Timing Requirements and Switching Characteristics
Parameter Symbol Min Max Units
Stabilization time
t
L–15µs
Input clock slew rate
slr(i) 1 4 V/ns
SSC modulation frequency
–3033kHz
SSC clock input frequency deviation
– 0 –0.5 %
PLL loop bandwidth (–3dB from unity gain)
–2 –MHz
PDF: 09005aef82d283a8/Source: 09005aef82d28271 Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTS72C1Gx72.fm - Rev. A 8/07 EN
11 ©2007 Micron Technology, Inc. All rights reserved.
8GB (x72, ECC, QR) 240-Pin DDR2 SDRAM RDIMM
Serial Presence-Detect
Serial Presence-Detect
Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.
Table 12: Serial Presence-Detect EEPROM DC Operating Conditions
Parameter/Condition Symbol Min Max Units
Supply voltage
V
DDSPD 1.7 3.6 V
Input high voltage: Logic 1; All inputs
V
IH VDDSPD × 0.7 VDDSPD + 0.5 V
Input low voltage: Logic 0; All inputs
V
IL –0.6 VDDSPD × 0.3 V
Output low voltage: I
OUT = 3mA
VOL –0.4V
Input leakage current: V
IN = GND to VDD
ILI 0.1 3 µA
Output leakage current: V
OUT = GND to VDD
ILO 0.05 3 µA
Standby current
I
SB 1.6 4 µA
Power supply current, READ: SCL clock frequency = 100 kHz
I
CC
R
0.4 1 mA
Power supply current, WRITE: SCL clock frequency = 100 kHz
I
CC
W
23mA
Table 13: Serial Presence-Detect EEPROM AC Operating Conditions
Parameter/Condition Symbol Min Max Units Notes
SCL LOW to SDA data-out valid
t
AA 0.2 0.9 µs 1
Time the bus must be free before a new transition can start
t
BUF 1.3 – µs
Data-out hold time
t
DH 200 – ns
SDA and SCL fall time
t
F–300ns2
Data-in hold time
t
HD:DAT 0 – µs
Start condition hold time
t
HD:STA 0.6 – µs
Clock HIGH period
t
HIGH 0.6 – µs
Noise suppression time constant at SCL, SDA inputs
t
I–50ns
Clock LOW period
t
LOW 1.3 – µs
SDA and SCL rise time
t
R–0.3µs2
SCL clock frequency
f
SCL – 400 kHz
Data-in setup time
t
SU:DAT 100 – ns
Start condition setup time
t
SU:STA 0.6 – µs 3
Stop condition setup time
t
SU:STO 0.6 – µs
WRITE cycle time
t
WRC – 10 ms 4
PDF: 09005aef82d283a8/Source: 09005aef82d28271 Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTS72C1Gx72.fm - Rev. A 8/07 EN
12 ©2007 Micron Technology, Inc. All rights reserved.
8GB (x72, ECC, QR) 240-Pin DDR2 SDRAM RDIMM
Serial Presence-Detect
Table 14: Serial Presence-Detect Matrix
Byte Description Entry (Version) 8GB
0
Number of SPD bytes used by Micron
128 80
1
Total number of bytes in SPD device
256 08
2
Fundamental memory type
DDR2 SDRAM 08
3
Number of row addresses on SDRAM
14 0E
4
Number of column addresses on SDRAM
11 0B
5
DIMM height and module ranks
30mm, quad rank 63
6
Module data width
72 48
7
Reserved
000
8
Module voltage interface levels
SSTL 1.8V 05
9
SDRAM cycle time,
t
CK
(CL = MAX value, see byte 18)
-667
-53E
-40E
30
3D
50
10
SDRAM access from clock,
t
AC
(CL = MAX value, see byte 18)
-667
-53E
-40E
45
50
60
11
Module configuration type
ECC and parity 06
12
Refresh rate/type
7.81µs/SELF 82
13
SDRAM device width (primary SDRAM)
404
14
Error-checking SDRAM data width
404
15
Reserved
000
16
Burst lengths supported
4, 8 0C
17
Number of banks on SDRAM device
808
18
CAS latencies supported
-667 (5, 4, 3)
-53E/-40E (4, 3)
38
18
19
Module thickness (with/without heat spreader)
HTS/HTZS 01/04
20
DDR2 DIMM type
Registered DIMM 01
21
SDRAM module attributes
1 PLL, 2 Reg 05
22
SDRAM device attributes: weak driver (01) or weak driver and
50Ω ODT (03)
-667
-53E/-40E
03
01
23
SDRAM cycle time,
t
CK, MAX CL - 1
-667
-53E/-40E
3D
50
24
SDRAM access from CK,
t
AC, MAX CL - 1
-667
-53E
-40E
45
50
60
25
SDRAM access from CK,
t
AC, MAX CL - 1
-667
-53E/-40E
50
00
26
SDRAM access from CK,
t
AC, MAX CL - 2
-667
-53E/-40E
45
00
27
MIN row precharge time,
t
RP
–3C
28
MIN row active-to-row active,
t
RRD
–1E
29
MIN RAS#-to-CAS# delay,
t
RCD
–3C
30
MIN active-to-precharge time,
t
RAS
-667/-53E
-40E
2D
28
31
Module rank density
2GB 02
32
Address and command setup time,
t
IS
b
-667
-53E
-40E
20
25
35
P1-P3P4-P6P7-P9P10-P12P13-P15

MT72HTS1G72PY-53EE1

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Manufacturer:
Micron
Description:
MODULE DDR2 SDRAM 8GB 240RDIMM
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